C8051F010-GQ Silicon Laboratories Inc, C8051F010-GQ Datasheet

IC 8051 MCU 32K FLASH 64TQFP

C8051F010-GQ

Manufacturer Part Number
C8051F010-GQ
Description
IC 8051 MCU 32K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F01xr
Datasheets

Specifications of C8051F010-GQ

Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
4 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F005DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
336-1191

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F010-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
ANALOG PERIPHERALS
-
-
-
-
-
ON-CHIP JTAG DEBUG & BOUNDARY SCAN
-
-
-
-
-
-
Rev. 1.7 11/03
SAR ADC
Two 12-bit DACs
Two Analog Comparators
Voltage Reference
Precision VDD Monitor/Brown-out Detector
On-Chip Debug Circuitry Facilitates Full Speed, Non-
Intrusive In-System Debug (No Emulator Required!)
Provides Breakpoints, Single Stepping, Watchpoints, Stack
Monitor
Inspect/Modify Memory and Registers
Superior Performance to Emulation Systems Using ICE-
Chips, Target Pods, and Sockets
IEEE1149.1 Compliant Boundary Scan
Low Cost Development Kit
12-Bit (C8051F000/1/2, C8051F005/6/7)
10-bit (C8051F010/1/2, C8051F015/6/7)
1LSB INL; No Missing Codes
Programmable Throughput up to 100ksps
Up to 8 External Inputs; Programmable as Single-
Ended or Differential
Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
Data Dependent Windowed Interrupt Generator
Built-in Temperature Sensor ( 3C)
Programmable Hysteresis Values
Configurable to Generate Interrupts or Reset
2.4V; 15 ppm/C
Available on External Pin
ANALOG PERIPHERALS
ISP FLASH
12-Bit
12-Bit
8051 CPU
(25MIPS)
DAC
DAC
32KB
HIGH-SPEED CONTROLLER CORE
Copyright © 2003 by Silicon Laboratories
Mixed-Signal 32KB ISP FLASH MCU Family
SENSOR
PGA
TEMP
VREF
256/2304 B
SRAM
+
-
CIRCUIT
CLOCK
COMPARATORS
VOLTAGE
ADC
SAR
+
-
INTERRUPTS
HIGH SPEED 8051 C CORE
-
-
-
MEMORY
-
-
-
DIGITAL PERIPHERALS
-
-
-
-
-
-
CLOCK SOURCES
-
-
-
SUPPLY VOLTAGE ........................ 2.7V to 3.6V
-
-
64-Pin TQFP, 48-Pin TQFP, 32-Pin LQFP
Temperature Range: –40C to +85C
JTAG
Pipelined Instruction Architecture; Executes 70% of
Instruction Set in 1 or 2 System Clocks
Up to 25MIPS Throughput with 25MHz Clock
21 Vectored Interrupt Sources
256 Bytes Internal Data RAM (F000/01/02/10/11/12)
2304 Bytes Internal Data RAM (F005/06/07/15/16/17)
32k Bytes FLASH; In-System Programmable in 512 byte
Sectors
4 Byte-Wide Port I/O; All are 5V tolerant
Hardware SMBus
Serial Ports Available Concurrently
Programmable 16-bit Counter/Timer Array with Five
Capture/Compare Modules
Four General Purpose 16-bit Counter/Timers
Dedicated Watch-Dog Timer
Bi-directional Reset
Internal Programmable Oscillator: 2-to-16MHz
External Oscillator: Crystal, RC,C, or Clock
Can Switch Between Clock Sources on-the-fly; Useful in
Power Saving Modes
Typical Operating Current: 12.5mA @ 25MHz
Multiple Power Saving Sleep and Shutdown Modes
21
SPI Bus
Timer 0
Timer 1
Timer 2
Timer 3
DIGITAL I/O
SMBus
UART
PCA
CIRCUITRY
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
DEBUG
CONTROL
SANITY
TM
(I2C
TM
Compatible), SPI
TM
, and UART

Related parts for C8051F010-GQ

C8051F010-GQ Summary of contents

Page 1

... Mixed-Signal 32KB ISP FLASH MCU Family ANALOG PERIPHERALS - SAR ADC  12-Bit (C8051F000/1/2, C8051F005/6/7)  10-bit (C8051F010/1/2, C8051F015/6/7) 1LSB INL; No Missing Codes   Programmable Throughput up to 100ksps  External Inputs; Programmable as Single- Ended or Differential  Programmable Amplifier Gain: 16 0.5  ...

Page 2

... Figure 5.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F00x)...........................................36 Figure 5.14. 12-Bit ADC Window Interrupt Examples, Right Justified Data...................................................37 Figure 5.15. 12-Bit ADC Window Interrupt Examples, Left Justified Data .....................................................37 Figure 5.15. 12-Bit ADC Window Interrupt Examples, Left Justified Data .....................................................38 C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Rev. 1.7 2 ...

Page 3

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Table 5.1. 12-Bit ADC Electrical Characteristics..............................................................................................38 Table 5.1. 12-Bit ADC Electrical Characteristics..............................................................................................39 6. ADC (10-Bit, C8051F010/1/2/5/6/7 Only).......................................................................... 40 Figure 6.1. 10-Bit ADC Functional Block Diagram..........................................................................................40 6.1. Analog Multiplexer and PGA..................................................................................................................40 6.2. ADC Modes of Operation........................................................................................................................41 Figure 6.2. 10-Bit ADC Track and Conversion Example Timing.....................................................................41 Figure 6 ...

Page 4

... Priority Cross Bar Decoder................................................................................................................103 15.2. Port I/O Initialization.........................................................................................................................103 Figure 15.1. Port I/O Functional Block Diagram ............................................................................................104 Figure 15.2. Port I/O Cell Block Diagram.......................................................................................................104 Table 15.1. Crossbar Priority Decode .............................................................................................................105 Figure 15.3. XBR0: Port I/O CrossBar Register 0 ..........................................................................................106 C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Rev. 1.7 4 ...

Page 5

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 15.4. XBR1: Port I/O CrossBar Register 1 ..........................................................................................107 Figure 15.5. XBR2: Port I/O CrossBar Register 2 ..........................................................................................108 15.3. General Purpose Port I/O...................................................................................................................109 15.4. Configuring Ports Which are not Pinned Out....................................................................................109 Figure 15.6. P0: Port0 Register .......................................................................................................................109 Figure 15.7. PRT0CF: Port0 Configuration Register ......................................................................................109 Figure 15 ...

Page 6

... Figure 20.12. PCA0H: PCA Counter/Timer High Byte ..................................................................................163 Figure 20.13. PCA0CPLn: PCA Capture Module Low Byte ..........................................................................163 Figure 20.14. PCA0CPHn: PCA Capture Module High Byte.........................................................................163 21. JTAG (IEEE 1149.1) ......................................................................................................... 164 Figure 21.1. IR: JTAG Instruction Register ....................................................................................................164 21.1. Boundary Scan...................................................................................................................................165 C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Rev. 1.7 6 ...

Page 7

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Table 21.1. Boundary Data Register Bit Definitions.......................................................................................165 Figure 21.2. DEVICEID: JTAG Device ID Register ......................................................................................166 21.2. Flash Programming Commands.........................................................................................................167 Figure 21.3. FLASHCON: JTAG Flash Control Register...............................................................................168 Figure 21.4. FLASHADR: JTAG Flash Address Register..............................................................................168 Figure 21.5. FLASHDAT: JTAG Flash Data Register....................................................................................169 Figure 21 ...

Page 8

... C8051F010 20 32k 256  C8051F011 20 32k 256  C8051F012 20 32k 256  C8051F015 25 32k 2304  C8051F016 25 32k 2304  C8051F017 25 32k 2304 C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7    100 8    100 8    100 4    ...

Page 9

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 1.1. C8051F000/05/10/15 Block Diagram VDD VDD VDD Digital Power DGND DGND DGND AV+ AV+ Analog Power AGND AGND TCK Boundary Scan JTAG TMS TDI Logic Debug HW TDO /RST VDD WDT Monitor External XTAL1 Oscillator XTAL2 Circuit Internal Oscillator VREF ...

Page 10

... TMS Logic TDI Debug HW TDO /RST VDD WDT Monitor External XTAL1 Oscillator XTAL2 Circuit Internal Oscillator VREF VREF DAC0 DAC0 (12-Bit) C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 32kbyte 8 FLASH 0 256 byte RAM 5 Reset 2048 byte 1 XRAM (F006/16 only SFR Bus r System Clock e Rev. 1.7 C UART ...

Page 11

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 1.3. C8051F002/07/12/17 Block Diagram VDD VDD Digital Power DGND DGND AV+ AV+ Analog Power AGND AGND TCK Boundary Scan JTAG TMS Logic TDI Debug HW TDO /RST VDD WDT Monitor External XTAL1 Oscillator XTAL2 Circuit Internal Oscillator VREF VREF DAC0 ...

Page 12

... Instructions 26 Clocks to Execute 1 With the CIP-51’s maximum system clock at 25MHz, it has a peak throughput of 25MIPS. Figure 1.4 shows a comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system clocks. Figure 1.4. Comparison of Peak MCU Execution Speeds C8051F000/1/2/5/6/7 C8051F010/1/2/5/6 2/3 3 3/4 ...

Page 13

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 1.1.3. Additional Features The C8051F000 MCU family has several key enhancements both inside and outside the CIP-51 core to improve its overall performance and ease of use in the end applications. The extended interrupt handler provides 21 interrupt sources into the CIP-51 (as opposed to 7 for the standard 8051), allowing the numerous analog and digital peripherals to interrupt the controller ...

Page 14

... Byte ISP FLASH 0x8000 0x7FFF RESERVED 0x7E00 0x7DFF FLASH (In-System Programmable in 512 Byte Sectors) 0x0000 C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 DATA MEMORY INTERNAL DATA ADDRESS SPACE 0xFF Upper 128 RAM Special Function (Indirect Addressing Register's Only) (Direct Addressing Only) 0x80 0x7F (Direct and Indirect ...

Page 15

... All the peripherals (except for the ADC) are stalled when the MCU is halted, during single stepping breakpoint in order to keep them in sync. The C8051F000DK, C8051F005DK, C8051F010DK, and C8051F015DK are development kits with all the hardware and software necessary to develop application code and perform in-circuit debug with the C8051F000/1/2, F005/6/7, F010/1/2, and F015/6/7 MCUs respectively. The kit includes software with a developer’ ...

Page 16

... Priority SPI UART PCA Comptr. Outputs T0, T1, T2 Lowest SYSCLK Priority CNVSTR 8 P0 (P0.0-P0. (P1.0-P1.7) Port 8 Latches P2 (P2.0-P2. (P3.0-P3.7) C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 2 XBR0, XBR1, PRT0CF, PRT1CF, XBR2 Registers PRT2CF Registers 4 2 Priority Decoder I/O 2 Cells Digital Crossbar I/O Cells P2 8 I/O Cells PRT3CF ...

Page 17

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 1.5. Programmable Counter Array The C8051F000 MCU family has an on-board Programmable Counter/Timer Array (PCA) in addition to the four 16-bit general-purpose counter/timers. The PCA consists of a dedicated 16-bit counter/timer timebase with 5 programmable capture/compare modules. The timebase gets its clock from one of four sources: the system clock divided by 12, the system clock divided by 4, Timer 0 overflow External Clock Input (ECI) ...

Page 18

... With a maximum throughput of 100ksps, the ADC offers true 12-bit accuracy with an INL of 1LSB. The ADC in the C8051F010/1/2/5/6/7 is similar, but with 10-bit resolution. Each ADC has a maximum throughput of 100ksps. Each ADC has an INL of 1LSB, offering true 12-bit accuracy with the C8051F00x, and true 10-bit accuracy with the C8051F01x ...

Page 19

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 1.8. Comparators and DACs The C8051F000 MCU Family has two 12-bit DACs and two comparators on chip (the second comparator, CP1, is not bonded out on the F002, F007, F012, and F017). The MCU data and control interface to each comparator and DAC is via the Special Function Registers. The MCU can place any DAC or comparator in low power shutdown mode ...

Page 20

... Temperature Range SYSCLK (System Clock C8051F005/6/7, C8051F015/6/7 Frequency) (Note 2) SYSCLK (System Clock C8051F000/1/2, C8051F010/1/2 Frequency) (Note 2) Tsysl (SYSCLK Low Time) Tsysh (SYSCLK High Time) Note 1: Analog Supply AV+ must be greater than 1V for VDD monitor to operate. Note 2: SYSCLK must be at least 32 kHz to enable debugging. ...

Page 21

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 4. PINOUT AND PACKAGE DEFINITIONS Pin Numbers F000 F001 F002 Name Type F005 F006 F007 F010 F011 F012 F015 F016 F017 VDD 31, 23, 18, 40 DGND 30, 22, 17, 41, 33 27, 19 AV+ 16, 13 AGND 5, 44 TCK TMS TDI TDO D Out XTAL1 XTAL2 A Out ...

Page 22

... P3.6 D I/O 46 P3.7 D I/O 45 C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Description Analog Mux Channel Input 6. (See ADC Specification for complete description). Analog Mux Channel Input 7. (See ADC Specification for complete description). Port0 Bit0. (See the Port I/O Sub-System section for complete description). Port0 Bit1. (See the Port I/O Sub-System section for complete description). ...

Page 23

... CP1+ 2 CP0- 3 CP0+ 4 AGND 5 VRE F 6 AIN0 7 AIN1 8 AIN2 9 AIN3 10 AIN4 11 12 AIN5 AIN6 13 AIN7 14 AGND 15 AV C8051F000 43 42 C8051F005 41 C8051F010 40 39 C8051F015 Rev. 1.7 P0.3 P0.2 P3.6 P3.7 P2.6 P2.7 P0.1 DGND VD D P0.0 P1.0 P1.1 P1.2 P1.3 P1.4 P2.0 ...

Page 24

... Figure 4.2. TQFP-64 Package Drawing PIN 1 DESIGNATOR C8051F000/1/2/5/6/7 C8051F010/1/2/5/6 Rev. 1.7 MIN NOM (mm) ( 0.17 0. 12. 10. 0. ...

Page 25

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 4.3. TQFP-48 Pinout Diagram CP0- 1 CP0+ 2 VREF 3 AIN0 4 AIN1 5 AIN2 6 AIN3 7 AIN4 8 AIN5 9 AIN6 10 AIN7 11 AGND 12 25 C8051F001 C8051F006 C8051F011 C8051F016 Rev. 1.7 P0.3 36 P0.2 35 P0.1 34 DGND 33 VDD 32 P0.0 31 P1.0 30 P1.1 29 P1.2 28 DGND 27 P1.3 26 P1.4 25 ...

Page 26

... Figure 4.4. TQFP-48 Package Drawing PIN 1 IDENTIFIER C8051F000/1/2/5/6/7 C8051F010/1/2/5/6 Rev. 1.7 MIN NOM MAX (mm) (mm) (mm 1.20 0.05 - 0.15 0.95 1.00 1.05 0.17 0.22 0. ...

Page 27

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 4.5. LQFP-32 Pinout Diagram 1 CP0- CP0+ 2 VREF 3 4 AIN0 AIN1 5 6 AIN2 AIN3 7 8 AGND 27 C8051F002 C8051F007 C8051F012 C8051F017 Rev. 1.7 24 P0.3 23 P0.2 22 P0.1 21 DGND 20 VDD 19 P0.0 18 VDD 17 DGND ...

Page 28

... Figure 4.6. LQFP-32 Package Drawing PIN 1 IDENTIFIER C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 MIN (mm 0. 1. Rev. 1.7 NOM MAX (mm) (mm 1.60 - 0.15 1.40 1.45 0.37 0. ...

Page 29

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 5. ADC (12-Bit, C8051F000/1/2/5/6/7 Only) The ADC subsystem for the C8051F000/1/2/5/6/7 consists of a 9-channel, configurable analog multiplexer (AMUX), a programmable gain amplifier (PGA), and a 100ksps, 12-bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector (see block diagram in Figure 5.1). The AMUX, PGA, Data Conversion Modes, and Window Detector are all configurable under software control via the Special Function Register’ ...

Page 30

... CNVSTR (ADSTM[1:0]=10) SAR Clocks Low Power or ADCTM=1 Convert ADCTM=0 B. ADC Timing for Internal Trigger Sources Timer2, Timer3 Overflow; Write 1 to ADBUSY (ADSTM[1:0]=00, 01, 11) SAR Clocks Low Power or ADCTM=1 Convert SAR Clocks ADCTM=0 Track or Convert C8051F000/1/2/5/6/7 C8051F010/1/2/5/6 Track Convert Convert Track Or Convert ...

Page 31

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 5.3. Temperature Sensor Transfer Function (Volts) 1.000 0.900 0.800 0.700 0.600 0.500 -50 Figure 5.4. AMX0CF: AMUX Configuration Register (C8051F00x) R/W R/W R Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bit3: AIN67IC: AIN6, AIN7 Input Pair Configuration Bit ...

Page 32

... AIN0 AIN1 +(AIN0) 1011 -(AIN1) 1100 AIN0 AIN1 +(AIN0) 1101 -(AIN1) 1110 AIN0 AIN1 +(AIN0) 1111 -(AIN1) C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W - AMXAD3 AMXAD2 Bit4 Bit3 Bit2 AMXAD3-0 0010 0011 0100 0101 AIN2 AIN3 AIN4 AIN5 AIN2 AIN3 ...

Page 33

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 5.6. ADC0CF: ADC Configuration Register (C8051F00x) R/W R/W R/W ADCSC2 ADCSC1 ADCSC0 Bit7 Bit6 Bit5 Bits7-5: ADCSC2-0: ADC SAR Conversion Clock Period Bits 000: SAR Conversion Clock = 1 System Clock 001: SAR Conversion Clock = 2 System Clocks 010: SAR Conversion Clock = 4 System Clocks ...

Page 34

... ADC Window Comparison Data match has not occurred 1: ADC Window Comparison Data match occurred Bit0: ADLJST: ADC Left Justify Data Bit 0: Data in ADC0H:ADC0L Registers is right justified 1: Data in ADC0H:ADC0L Registers is left justified C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W ADBUSY ADSTM1 ADSTM0 ADWINT ...

Page 35

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 5.8. ADC0H: ADC Data Word MSB Register (C8051F00x) R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: ADC Data Word Bits For ADLJST = 1: Upper 8-bits of the 12-bit ADC Data Word. For ADLJST = 0: Bits7-4 are the sign extension of Bit3. Bits 3-0 are the upper 4-bits of the 12-bit ADC Data Word ...

Page 36

... Figure 5.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F00x) R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: These bits are the low byte of the ADC Less-Than Data Word. Definition: ADC Less-Than Data Word = ADC0LTH:ADC0LTL C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W Bit4 Bit3 Bit2 R/W R/W R/W Bit4 Bit3 ...

Page 37

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 5.14. 12-Bit ADC Window Interrupt Examples, Right Justified Data Input Voltage ADC Data (AD0 - AGND) Word REF x (4095/4096) 0x0FFF ADWINT not affected 0x0201 REF x (512/4096) 0x0200 ADC0LTH:ADC0LTL 0x01FF ADWINT=1 0x0101 REF x (256/4096) 0x0100 ADC0GTH:ADC0GTL 0x00FF ADWINT not affected ...

Page 38

... AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 1, ADC0LTH:ADC0LTL = 0x1000, ADC0GTH:ADC0GTL = 0xFFF0. An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x1000 and > 0xFFF0. Complement math.) C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Input Voltage ADC Data (AD0 - AGND) Word REF x (4095/4096) 0xFFF0 0x2010 ...

Page 39

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Table 5.1. 12-Bit ADC Electrical Characteristics VDD = 3.0V, AV+ = 3.0V, VREF = 2.40V (REFBE=0), PGA Gain = 1, -40C to +85C unless otherwise specified. PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Offset Error Full Scale Error Differential mode Offset Temperature Coefficient DYNAMIC PERFORMANCE (10kHz sine-wave input – ...

Page 40

... ADC (10-Bit, C8051F010/1/2/5/6/7 Only) The ADC subsystem for the C8051F010/1/2/5/6/7 consists of a 9-channel, configurable analog multiplexer (AMUX), a programmable gain amplifier (PGA), and a 100ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector (see block diagram in Figure 6.1). The AMUX, PGA, Data Conversion Modes, and Window Detector are all configurable under software control via the Special Function Register’ ...

Page 41

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 6.2. ADC Modes of Operation The ADC uses VREF to determine its full-scale voltage, thus the reference must be properly configured before performing a conversion (see Section 9). The ADC has a maximum conversion speed of 100ksps. The ADC conversion clock is derived from the system clock. Conversion clock speed can be reduced by a factor via the ADCSC bits in the ADC0CF Register ...

Page 42

... AIN01IC: AIN0, AIN1 Input Pair Configuration Bit 0: AIN0 and AIN1 are independent singled-ended inputs 1: AIN0, AIN1 are (respectively differential input pair NOTE: The ADC Data Word is in 2’s complement format for channels configured as differential. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6 0.00286(TEMP TEMP for PGA Gain = 1 ...

Page 43

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 6.5. AMX0SL: AMUX Channel Select Register (C8051F01x) R/W R/W R Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care Bits3-0: AMXAD3-0: AMUX Address Bits 0000-1111: ADC Inputs selected per chart below 0000 0001 A 0000 AIN0 AIN1 M X +(AIN0) ...

Page 44

... Conversion clock should be  2MHz.) Bits4-3: UNUSED. Read = 00b; Write = don’t care Bits2-0: AMPGN2-0: ADC Internal Amplifier Gain 000: Gain = 1 001: Gain = 2 010: Gain = 4 011: Gain = 8 10x: Gain = 16 11x: Gain = 0.5 C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W R AMPGN2 AMPGN1 Bit4 ...

Page 45

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 6.7. ADC0CN: ADC Control Register (C8051F01x) R/W R/W R/W ADCEN ADCTM ADCINT Bit7 Bit6 Bit5 Bit7: ADCEN: ADC Enable Bit 0: ADC Disabled. ADC is in low power shutdown. 1: ADC Enabled. ADC is active and ready for data conversions. Bit6: ADCTM: ADC Track Mode Bit ...

Page 46

... EXAMPLE: ADC Data Word Conversion Map, AIN0-AIN1 Differential Input Pair (AMX0CF=0x01, AMX0SL=0x00) ADC0H:ADC0L AIN0 – AIN1 (Volts) (ADLJST = 0) REF x (511/512) 0x01FF 0 0x0000 -REF x (1/512) 0xFFFF -REF 0xFE00 C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W Bit4 Bit3 Bit2 R/W R/W R/W Bit4 Bit3 Bit2 ADC0H:ADC0L ...

Page 47

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 6.3. ADC Programmable Window Detector The ADC programmable window detector is very useful in many applications. It continuously compares the ADC output to user-programmed limits and notifies the system when an out-of-band condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster system response times ...

Page 48

... AMX0SL = 0x00, AMX0CF = 0x01, ADLJST = 0, ADC0LTH:ADC0LTL = 0x0100, ADC0GTH:ADC0GTL = 0xFFFF. An ADC End of Conversion will cause an ADC Window Compare Interrupt (ADWINT=1) if the resulting ADC Data Word is < 0x0100 and > 0xFFFF. Complement math, 0xFFFF = -1.) C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Input Voltage ADC Data (AD0 - AGND) Word REF x (1023/1024) 0x03FF 0x0201 ...

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... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 6.15. 10-Bit ADC Window Interrupt Examples, Left Justified Data Input Voltage ADC Data (AD0 - AGND) Word REF x (1023/1024) 0xFFC0 ADWINT not affected 0x8040 REF x (512/1024) 0x8000 ADC0LTH:ADC0LTL 0x7FC0 ADWINT=1 0x4040 REF x (256/1024) 0x4000 ADC0GTH:ADC0GTL 0x3FC0 ADWINT not affected ...

Page 50

... Gain Error (1) Offset PGA Gain = 1, Temp = 0C Offset Error (1) PGA Gain = 1, Temp = 0C POWER SPECIFICATIONS Power Supply Current (AV+ Operating Mode, 100ksps supplied to ADC) Power Supply Rejection C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 CONDITIONS MIN 59 th harmonic 16 1.5 0 AGND Rev. 1.7 TYP ...

Page 51

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 7. DACs, 12 BIT VOLTAGE MODE The C8051F000 MCU family has two 12-bit voltage-mode Digital to Analog Converters. Each DAC has an output swing VREF-1LSB for a corresponding input code range of 0x000 to 0xFFF. Using DAC0 as an example, the 12-bit data word is written to the low byte (DAC0L) and high byte (DAC0H) data registers. Data is latched into DAC0 after a write to the corresponding DAC0H register, so the write sequence should be DAC0L followed by DAC0H if the full 12-bit resolution is required ...

Page 52

... The most significant 7-bits of the DAC0 Data Word is in DAC0H[6:0], while the least significant 5-bits is in DAC0L[7:3]. DAC0H MSB 1xx: The most significant byte of the DAC0 Data Word is in DAC0H, while the least significant nybble is in DAC0L[7:4]. DAC0H MSB C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W R/W Bit4 Bit3 Bit2 R/W ...

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... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 7.5. DAC1H: DAC1 High Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC1 Data Word Most Significant Byte. Figure 7.6. DAC1L: DAC1 Low Byte Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DAC1 Data Word Least Significant Byte. ...

Page 54

... Output Voltage Swing Startup Time DAC Enable asserted ANALOG OUTPUTS Load Regulation I = 0.01mA to 0.3mA at code 0xFFF L CURRENT CONSUMPTION (each DAC) Power Supply Current (AV+ Data Word = 0x7FF supplied to DAC) C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 CONDITIONS MIN 0 Rev. 1.7 TYP MAX UNITS 12 bits 2 LSB 1 LSB  ...

Page 55

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 8. COMPARATORS The MCU family has two on-chip analog voltage comparators as shown in Figure 8.1. The inputs of each Comparator are available at the package pins. The output of each comparator is optionally available at the package pins via the I/O crossbar (see Section 15.1). When assigned to package pins, each comparator output can be programmed to operate in open drain or push-pull modes (see section 15 ...

Page 56

... VIN+ + CP0 CP0- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYSP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 OUT Negative Hysteresis Disabled Maximum Positive Hysteresis Rev. 1.7 Negative Hysteresis Voltage (Programmed by CP0HYSN Bits) Maximum Negative Hysteresis 56 ...

Page 57

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 8.3. CPT0CN: Comparator 0 Control Register R/W R R/W CP0EN CP0OUT CP0RIF Bit7 Bit6 Bit5 Bit7: CP0EN: Comparator 0 Enable Bit 0: Comparator 0 Disabled. 1: Comparator 0 Enabled. Bit6: CP0OUT: Comparator 0 Output State Flag 0: Voltage on CP0+ < CP0- 1: Voltage on CP0+ > CP0- Bit5: CP0RIF: Comparator 0 Rising-Edge Interrupt Flag ...

Page 58

... Positive Hysteresis Disabled 01: Positive Hysteresis = 2mV 10: Positive Hysteresis = 4mV 11: Positive Hysteresis = 10mV Bit1-0: CP1HYN1-0: Comparator 1 Negative Hysteresis Control Bits 00: Negative Hysteresis Disabled 01: Negative Hysteresis = 2mV 10: Negative Hysteresis = 4mV 11: Negative Hysteresis = 10mV C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 Bit4 Bit3 Bit2 Rev ...

Page 59

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Table 8.1. Comparator Electrical Characteristics VDD = 3.0V, AV+ = 3.0V, -40C to +85C unless otherwise specified. PARAMETER Response Time1 (CP+) – (CP-) = 100mV (Note 1) Response Time2 (CP+) – (CP-) = 10mV (Note 1) Common Mode Rejection Ratio Positive Hysteresis1 CPnHYP1 Positive Hysteresis2 CPnHYP1 Positive Hysteresis3 CPnHYP1 Positive Hysteresis4 ...

Page 60

... A/D measurements performed on the sensor while disabled result in meaningless data. Figure 9.1. Voltage Reference Functional Block Diagram AV+ External Voltage Reference R1 Circuit AGND VREF External Equivalent Load Circuit RLOAD AGND C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Temp EN Sensor Bias EN TEMPE BIASE Generator REFBE AGND 2.4V EN Reference AGND Rev. 1.7 ...

Page 61

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 9.2. REF0CN: Reference Control Register R/W R/W R Bit7 Bit6 Bit5 Bits7-3: UNUSED. Read = 00000b; Write = don’t care Bit2: TEMPE: Temperature Sensor Enable Bit 0: Internal Temperature Sensor Off. 1: Internal Temperature Sensor On. Bit1: BIASE: Bias Enable Bit for ADC and DAC’s 0: Internal Bias Off. 1: Internal Bias On (required for use of ADC or DAC’ ...

Page 62

... ACCUMULATOR PSW DATA POINTER PC INCREMENTER PROGRAM COUNTER (PC) PRGM. ADDRESS REG. CONTROL RESET LOGIC CLOCK STOP POWER CONTROL IDLE REGISTER C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 - Reset Input - Power Management Modes - On-chip Debug Circuitry - Program and Data Memory Security DATA BUS B REGISTER TMP1 TMP2 SRAM ADDRESS ...

Page 63

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to execute, and usually have a maximum system clock of 12MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. With the CIP-51’ ...

Page 64

... Refer to Section 11 (Flash Memory) for further details. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Rev. 1.7 64 ...

Page 65

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Table 10.1. CIP-51 Instruction Set Summary Mnemonic Description ADD A,Rn Add register to A ADD A,direct Add direct byte to A ADD A,@Ri Add indirect RAM to A ADD A,#data Add immediate to A ADDC A,Rn Add register to A with carry ADDC A,direct ...

Page 66

... Jump if carry is set JNC rel Jump if carry not set JB bit,rel Jump if direct bit is set JNB bit,rel Jump if direct bit is not set JBC bit,rel Jump if direct bit is set and clear bit PROGRAM BRANCHING C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 DATA TRANSFER Rev. 1.7 Clock Bytes Cycles ...

Page 67

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Mnemonic Description ACALL addr11 Absolute subroutine call LCALL addr16 Long subroutine call RET Return from subroutine RETI Return from interrupt AJMP addr11 Absolute jump LJMP addr16 Long jump SJMP rel Short jump (relative address) JMP @A+DPTR Jump indirect relative to DPTR ...

Page 68

... The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where XX is the byte address and B is the bit position within the byte. For example, the instruction: MOV C, 22h.3 moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the user Carry flag. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Rev. 1.7 68 ...

Page 69

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 PROGRAM MEMORY 0x807F 128 Byte ISP FLASH 0x8000 0x7FFF RESERVED 0x7E00 0x7DFF FLASH (In-System Programmable in 512 Byte Sectors) 0x0000 10.2.5. Stack A programmer’s stack can be located anywhere in the 256-byte data memory. The stack area is designated using the Stack Pointer (SP, 0x81) SFR. The SP will point to the last location used. The next value pushed on the stack is placed at SP+1 and then SP is incremented ...

Page 70

... Bit Addressable Table 10.3. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved. * Refers to a register in the C8051F000/1/2/5/6/7 only. ** Refers to a register in the C8051F010/1/2/5/6/7 only. *** Refers to a register in the C8051F005/06/07/15/16/17 only. Description Address Register 0xE0 ...

Page 71

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Address Register Description 0xC7 ADC0LTH ADC Less-Than Data Word (High Byte) 0xC6 ADC0LTL ADC Less-Than Data Word (Low Byte) 0xBA AMX0CF ADC MUX Configuration 0xBB AMX0SL ADC MUX Channel Selection 0xF0 B B Register 0x8E CKCON Clock Control 0x9E CPT0CN ...

Page 72

... TH2 Counter/Timer 2 Data Word (High Byte) 0x8A TL0 Counter/Timer 0 Data Word (Low Byte) 0x8B TL1 Counter/Timer 1 Data Word (Low Byte) 0xCC TL2 Counter/Timer 2 Data Word (Low Byte) C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Rev. 1.7 Page No. 163 162 162 162 162 162 163 163 161 ...

Page 73

... Port I/O Crossbar Configuration 3 0x84-86, 0x96-97, 0x9C, 0xA1-A3, 0xA9-AC, 0xAE, 0xB3-B5, 0xB9, Reserved 0xBD, 0xC9, 0xCE, 0xDF, 0xE4-E5, 0xF1-F5 * Refers to a register in the C8051F000/1/2/5/6/7 only. ** Refers to a register in the C8051F010/1/2/5/6/7 only. *** Refers to a register in the C8051F005/06/07/15/16/17 only. 73 Rev. 1.7 Page No. 143 152 153 ...

Page 74

... R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: DPH: Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed RAM and Flash Memory. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W Bit4 Bit3 Bit2 R/W R/W R/W ...

Page 75

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 10.6. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation results in a carry (addition borrow (subtraction cleared all other arithmetic operations. Bit6: AC: Auxiliary Carry Flag. This bit is set when the last arithmetic operation results in a carry into (addition borrow from (subtraction) the high order nibble ...

Page 76

... This register is the accumulator for arithmetic operations. Figure 10. Register R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits 7- Register This register serves as a second accumulator for certain arithmetic operations. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W ACC.4 ACC.3 ACC.2 Bit4 Bit3 Bit2 R/W R/W R/W B.4 B ...

Page 77

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 10.4. INTERRUPT HANDLER The CIP-51 includes an extended interrupt system supporting a total of 22 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific version of the device. Each interrupt source has one or more associated interrupt-pending flag(s) located in an SFR ...

Page 78

... LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and following instruction. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Priority Interrupt-Pending Flag Order Top ...

Page 79

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 10.4.5. Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). ...

Page 80

... Timer 0 interrupt set to high priority level. Bit0: PX0: External Interrupt 0 Priority Control. This bit sets the priority of the External Interrupt 0 interrupts. 0: External Interrupt 0 set to low priority level. 1: External Interrupt 0 set to high priority level. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W PS PT1 PX1 Bit4 ...

Page 81

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 10.11. EIE1: Extended Interrupt Enable 1 R/W R/W R/W ECP1R ECP1F ECP0R Bit7 Bit6 Bit5 Bit7: ECP1R: Enable Comparator 1 (CP1) Rising Edge Interrupt. This bit sets the masking of the CP1 interrupt. 0: Disable CP1 Rising Edge interrupt. 1: Enable interrupt requests generated by the CP1RIF flag (CPT1CN.5). ...

Page 82

... Enable interrupt requests generated by the ADC0 Conversion Interrupt. Bit0: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable all Timer 3 interrupts. 1: Enable interrupt requests generated by the TF3 flag (TMR3CN.7) C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W EX6 EX5 EX4 ...

Page 83

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 10.13. EIP1: Extended Interrupt Priority 1 R/W R/W R/W PCP1R PCP1F PCP0R Bit7 Bit6 Bit5 Bit7: PCP1R: Comparator 1 (CP1) Rising Interrupt Priority Control. This bit sets the priority of the CP1 interrupt. 0: CP1 rising interrupt set to low priority level. 1: CP1 rising interrupt set to high priority level. ...

Page 84

... ADC0 End of Conversion interrupt set to high priority level. Bit0: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupts. 0: Timer 3 interrupt set to low priority level. 1: Timer 3 interrupt set to high priority level. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W PX6 PX5 PX4 ...

Page 85

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 10.5. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the external peripherals and internal clocks active. In Stop mode, the CPU is halted, all interrupts and timers (except the Missing Clock Detector) are inactive, and the system clock is stopped. Since clocks are running in Idle mode, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering Idle ...

Page 86

... IDLE: Idle Mode Select. Setting this bit will place the CIP-51 in Idle mode. This bit will always be read Goes into idle mode. (Shuts off clock to CPU, but clock to Timers, Interrupts, Serial Ports, and Analog Peripherals are still active.) C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W GF2 ...

Page 87

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 11. FLASH MEMORY These devices include 32k + 128 bytes of on-chip, reprogrammable Flash memory for program code and non- volatile data storage. The Flash memory can be programmed in-system, a single byte at a time, through the JTAG interface or by software using the MOVX instruction. Once cleared Flash bit must be erased to set it back to 1 ...

Page 88

... Setting this bit allows writing a byte of data to the Flash program memory using the MOVX instruction. The location must be erased before writing data. 0: Write to Flash program memory disabled. 1: Write to Flash program memory enabled. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 The Program Store Write Enable R/W R/W R/W ...

Page 89

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 11.2. Flash Program Memory Security Bytes Program Memory Space FLASH Read Lock Byte Bits7-0: Each bit locks a corresponding block of memory. (Bit 7 is MSB.) 0: Read operations are locked (disabled) for corresponding block across the JTAG interface. 1: Read operations are unlocked (enabled) for corresponding block across the JTAG interface. ...

Page 90

... The entire 16-bit access limit address value is calculated as 0xNN00 where NN is replaced by contents of FLACL. A write to this register sets the Flash Access Limit. This register can only be written once after any reset. Any subsequent writes are ignored until the next reset. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W Bit4 ...

Page 91

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 11.4. FLSCL: Flash Memory Timing Prescaler R/W R/W R/W FOSE FRAE - Bit7 Bit6 Bit5 Bit7: FOSE: Flash One-Shot Timer Enable 0: Flash One-shot timer disabled. 1: Flash One-shot timer enabled Bit6: FRAE: Flash Read Always Enable 0: Flash reads per one-shot timer 1: Flash always in read mode Bits5-4: UNUSED. Read = 00b, Write = don’ ...

Page 92

... RAM. The upper 5-bits are “don’t cares”, so the 2k address blocks are repeated modulo over the entire 64k external data memory address space. 000: xxxxx000b 001: xxxxx001b 010: xxxxx010b 011: xxxxx011b 100: xxxxx100b 101: xxxxx101b 110: xxxxx110b 111: xxxxx111b C8051F000/1/2/5/6/7 C8051F010/1/2/5/6 R/W R PGSEL2 PGSEL1 Bit4 Bit3 ...

Page 93

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 13. RESET SOURCES The reset circuitry of the MCUs allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the CIP-51 halts program execution, forces the external port pins to a known state and initializes the SFRs to their defined reset values. Interrupts and timers are disabled. On exit, the program counter (PC) is reset, and program execution starts at location 0x0000 ...

Page 94

... CIP-51 will leave the reset state in the same manner as that for the power-on reset. Note that even RST though internal data memory contents are not altered by the power-fail reset impossible to determine if VDD dropped below the level required for data retention. If the PORSF flag is set, the data may no longer be valid. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 100ms RST Rev. 1.7 t ...

Page 95

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 13.4. External Reset The external /RST pin provides a means for external circuitry to force the MCU into a reset state. Asserting an active-low signal on the /RST pin will cause the MCU to enter the reset state. Although there is a weak internal pullup, it may be desirable to provide an external pull-up and/or decoupling of the /RST pin to avoid erroneous noise-induced resets ...

Page 96

... Reading the WDTCN.[4] bit indicates the Watchdog Timer Status. 0: WDT is inactive 1: WDT is active Bits2-0: Watchdog Timeout Interval Bits The WDTCN.[2:0] bits set the Watchdog Timeout Interval. When writing these bits, WDTCN.7 must be set to 0. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 is the system clock period). SYSCLK R/W R/W R/W Bit4 ...

Page 97

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 13.4. RSTSRC: Reset Source Register R R/W R/W JTAGRST CNVRSEF C0RSEF Bit7 Bit6 Bit5 (Note: Do not use read-modify-write operations on this register.) Bit7: JTAGRST. JTAG Reset Flag. 0: JTAG is not currently in reset state. 1: JTAG is in reset state. Bit6: CNVRSEF: Convert Start Reset Source Enable and Flag ...

Page 98

... AV+ for /RST Output Valid VDD POR Threshold (V ) RST Reset Time Delay /RST rising edge after crossing reset threshold Missing Clock Detector Time from last system clock to reset Timeout generation C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 CONDITIONS MIN 0.7 x VDD 1.0 1.0 2.40 80 100 Rev. 1.7 TYP MAX UNITS 0 ...

Page 99

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 14. OSCILLATOR Each MCU includes an internal oscillator and an external oscillator drive circuit, either of which can generate the system clock. The MCUs boot from the internal oscillator after any reset. The internal oscillator starts up instantly. It can be enabled/disabled and its frequency can be changed using the Internal Oscillator Control Register (OSCICN) as shown in Figure 14.2. The internal oscillator’ ...

Page 100

... PARAMETER Internal Oscillator OSCICN.[1: Frequency OSCICN.[1: OSCICN.[1: OSCICN.[1: Internal Oscillator Current OSCICN Consumption (from VDD) Internal Oscillator Temperature Stability Internal Oscillator Power Supply (VDD) Stability C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R R/W R/W IFRDY CLKSL IOSCEN Bit4 Bit3 Bit2 CONDITIONS MIN 1.5 3.1 6.2 12.3 Rev ...

Page 101

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 14.3. OSCXCN: External Oscillator Control Register R R/W R/W XTLVLD XOSCMD2 XOSCMD1 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag (Valid only when XOSCMD = 1xx.) 0: Crystal Oscillator is unused or not yet stable 1: Crystal Oscillator is running and stable (should read 1ms after Crystal Oscillator is enabled to avoid transient condition) ...

Page 102

... Assume AV+ = 3.0V and C = 50pF VDD ( 150 If a frequency of roughly 90kHz is desired, select the K Factor from the table in Figure 14 13 /150 = 0.087MHz, or 87kHz Therefore, the XFCN value to use in this example is 011. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 (4) 2 Rev. 1.7 102 ...

Page 103

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 15. PORT INPUT/OUTPUT The MCUs have a wide array of digital resources, which are available through four digital I/O ports, P0, P1, P2 and P3. Each of the pins on Ports 0, 1, and 2 can be defined as either its corresponding port I/O or one of the internal digital resources assigned as shown in Figure 15.1. The designer has complete control over which functions are ...

Page 104

... P0 (P0.0-P0. (P1.0-P1.7) Port 8 Latches P2 (P2.0-P2. (P3.0-P3.7) Figure 15.2. Port I/O Cell Block Diagram WEAKPUD PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT PORT-INPUT C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 XBR0, XBR1, PRT0CF, PRT1CF, XBR2 Registers PRT2CF Registers Priority Decoder P0 8 I/O Cells Digital Crossbar P1 8 I/O Cells P2 8 I/O Cells ...

Page 105

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Table 15.1. Crossbar Priority Decode P0 PIN I  SDA  SCL   SCK   MISO   MOSI   NSS    TX    RX    CEX0    CEX1   CEX2  ...

Page 106

... SPI I/O unavailable at Port pins. 1: MISO, MOSI, SCK, and NSS routed to 4 Port Pins. Bit0: SMB0OEN: SMBus Bus I/O Enable Bit 0: SMBus I/O unavailable at P0.0, P0.1. 1: SDA routed to P0.0, SCL routed to P0.1. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W UARTEN SPI0OEN Bit4 Bit3 Bit2 Rev ...

Page 107

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 15.4. XBR1: Port I/O CrossBar Register 1 R/W R/W R/W SYSCKE T2EXE T2E Bit7 Bit6 Bit5 Bit7: SYSCKE: SYSCLK Output Enable Bit 0: SYSCLK unavailable at Port pin. 1: SYSCLK output routed to Port Pin. Bit6: T2EXE: T2EX Enable Bit 0: T2EX unavailable at Port pin. ...

Page 108

... Example1: If XBR0 = 0x11, XBR1 = 0x00, and XBR2 = 0x40: P0.0=SDA, P0.1=SCL, P0.2=CEX0, P0.3=CEX1, P0.4 … P2.7 map to corresponding Port I/O. Example2: If XBR0 = 0x80, XBR1 = 0x04, and XBR2 = 0x41: P0.0=CP0, P0.1=/INT0, P0.2 = CNVSTR, P0.3 … P2.7 map to corresponding Port I/O. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W - ...

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... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 15.3. General Purpose Port I/O Each MCU has four byte-wide, bi-directional parallel ports that can be used general purpose I/O. Each port is accessed through a corresponding special function register (SFR) that is both byte addressable and bit addressable. When writing to a port, the value written to the SFR is latched to maintain the output data value at each pin. When reading, the logic levels of the port’ ...

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... This flag is set by hardware when a falling edge on P1.5 is detected. Bit4: IE4: External Interrupt 4 Pending Flag falling edge detected on P1.4. 1: This flag is set by hardware when a falling edge on P1.4 is detected. Bits3-0: UNUSED. Read = 0000b, Write = don’t care. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W P1.4 P1.3 P1.2 ...

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... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 15.11. P2: Port2 Register R/W R/W R/W P2.7 P2.6 P2.5 Bit7 Bit6 Bit Bits7-0: P2.[7:0] (Write – Output appears on I/O pins per XBR0, XBR1, and XBR2 registers) 0: Logic Low Output. 1: Logic High Output (high-impedance if corresponding PRT2CF.n bit = 0) (Read – Regardless of XBR0, XBR1, and XBR2 Register settings). ...

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... 8.5mA 25mA OL Input High Voltage Input Low Voltage Input Leakage Current DGND < Port Pin < VDD, Pin Tri-state Weak Pull-up Off Weak Pull-up On Capacitive Loading C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W P3.4 P3.3 P3.2 Bit4 Bit3 Bit2 R/W R/W R/W Bit4 Bit3 Bit2 ...

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... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 16. SMBus / I2C Bus The SMBus serial I/O interface is compliant with the System Management Bus Specification, version 1. two-wire, bi-directional serial bus, which is also compatible with the I interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data ...

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... It is assumed the reader is familiar with or has access to the following supporting documents The I C-bus and how to use it (including specifications), Philips Semiconductor The I C-Bus Specification -- Version 2.0, Philips Semiconductor. 3. System Management Bus Specification -- Version 1.1, SBS Implementers Forum. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 VDD = 5V Master Slave Device Device 1 Rev. 1.7 VDD = 3V Slave ...

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... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 16.2. Operation A typical SMBus transaction consists of a START condition, followed by an address byte, one or more bytes of data, and a STOP condition. The address byte and each of the data bytes are followed by an ACKNOWLEDGE bit from the receiver. The address byte consists of a 7-bit address plus a direction bit. The direction bit (R/W) occupies the least-significant bit position of the address. The direction bit is set to logic 1 to indicate a “ ...

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... Clock Rate Register, SMB0ADR Address Register, SMB0DAT Data Register and SMB0STA Status Register. The system device may have one or more SMBus serial interfaces implemented. The five special function registers related to the operation of the SMBus interface are described in the following section. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Rev. 1.7 116 ...

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... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 16.6.1. Control Register The SMBus Control register SMB0CN is used to configure and control the SMBus interface. All of the bits in the register can be read or written by software. Two of the control bits are also affected by the SMBus hardware. The Serial Interrupt flag (SI, SMB0CN.3) is set to logic 1 by the hardware when a valid serial interrupt condition occurs. ...

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... No timeout when SCL is high 1: Timeout when SCL high time exceeds limit specified by the SMB0CR value. Bit0: TOE: SMBus Timeout Enable Bit 0: No timeout when SCL is low. 1: Timeout when SCL low time exceeds limit specified by Timer 3, if enabled. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W STO SI AA ...

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... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 16.6.2. Clock Rate Register Figure 16.5. SMB0CR: SMBus Clock Rate Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: SMB0CR.[7:0]: SMBus Clock Rate Preset The SMB0CR Clock Rate register controls the frequency of the serial clock SCL in master mode. The 8-bit word stored in the SMB0CR Register preloads a dedicated 8-bit timer. ...

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... SMBus. Bit0: GC: General Call Address Enable. This bit is used to enable general call address (0x00) recognition. 0: General call address is ignored. 1: General call address is recognized. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W Bit4 Bit3 Bit2 ...

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... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 16.6.5. Status Register The SMB0STA Status register holds an 8-bit status code indicating the current state of the SMBus. There are 28 possible SMBus states, each with a corresponding unique status code. The five most significant bits of the status code vary while the three least-significant bits of a valid status code are fixed at zero when Therefore, all possible status codes are multiples of eight ...

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... Slave Transmitter 0xD0 Slave Transmitter/Receiver 0xF8 All C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 SMBus State Bus Error (i.e. illegal START, illegal STOP, …) START condition transmitted. Repeated START condition transmitted. Slave address + W transmitted. ACK received. Slave address + W transmitted. NACK received. Data byte transmitted. ACK received. ...

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... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 17. SERIAL PERIPHERAL INTERFACE BUS The Serial Peripheral Interface (SPI) provides access to a four-wire, full-duplex, serial bus. SPI supports the connection of multiple slave devices to a master device on the same bus. A separate slave-select signal (NSS) is used to select a slave device and enable a data transfer between the master and the selected slave. Multiple masters on the same bus are also supported ...

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... The slave select (NSS) signal is an input used to select the SPI module when in slave mode by a master disable the SPI module when in master mode. When in slave mode pulled low to initiate a data transfer and remains low for the duration of the transfer. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 NSS NSS Slave ...

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... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 17.2. Operation Only a SPI master device can initiate a data transfer. The SPI is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.1). Writing a byte of data to the SPI data register (SPI0DAT) when in Master Mode starts a data transfer. The SPI master immediately shifts out the data serially on the MOSI line while providing the serial clock on SCK ...

Page 126

... The SPI Clock Rate Register (SPI0CKR) as shown in Figure 17.7 controls the master mode serial clock frequency. This register is ignored when operating in slave mode. Figure 17.4. Data/Clock Timing Diagram SCK (CKPOL = 0, CKPHA = 0) SCK (CKPOL = 0, CKPHA = 1) SCK (CKPOL = 1, CKPHA = 0) SCK (CKPOL = 1, CKPHA = 1) MSB MISO/MOSI NSS C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Rev. 1.7 Bit 1 LSB 126 ...

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... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 17.4. SPI Special Function Registers The SPI is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related to the operation of the SPI Bus are described in the following section. ...

Page 128

... NSS is high (slave disabled). Bit1: MSTEN: Master Mode Enable. 0: Disable master mode. Operate in slave mode. 1: Enable master mode. Operate as a master. Bit0: SPIEN: SPI Enable. This bit enables/disables the SPI. 0: SPI disabled. 1: SPI enabled. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R TXBSY SLVSEL MSTEN Bit4 Bit3 Bit2 Rev. 1.7 ...

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... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 17.7. SPI0CKR: SPI Clock Rate Register R/W R/W R/W SCR7 SCR6 SCR5 Bit7 Bit6 Bit5 Bits7-0: SCR7-SCR0: SPI Clock Rate These bits determine the frequency of the SCK output when the SPI module is configured for master mode operation. The SCK clock frequency is a divided down ...

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... Baud Rate Generation Logic Timer 1 1 Overflow SMOD TCLK 0 16 Timer 2 1 Overflow RCLK SYSCLK SMOD 12 C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Write to SBUF TB8 SET SBUF D Q CLR Zero Detector Shift Stop Bit Start Data Gen. Tx Control Clock Send 10 Tx IRQ 11 TI Serial SM0, SM1 ...

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... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 18.1. UART Operational Modes The UART provides four operating modes (one synchronous and three asynchronous) selected by setting configuration bits in the SCON register. These four modes offer different baud rates and communication protocols. The four modes are summarized in Table 18.1 below. Detailed descriptions follow. ...

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... T1_OVERFLOWRATE = T1CLK / (256 – TH1). For example, assume TMOD = 0x20. If T1M (CKCON.4) is logic 1, then the above equation becomes: T1_OVERFLOWRATE = (SYSCLK) / (256 – TH1). If T1M (CKCON.4) is logic 0, then the above equation becomes: T1_OVERFLOWRATE = (SYSCLK/12) / (256 – TH1). C8051F000/1/2/5/6/7 C8051F010/1/2/5/6 Rev. 1.7 STOP ...

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... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 The Timer 2 overflow rate, when in Baud Rate Generator Mode and using an internal clock source, is determined solely by the Timer 2 16-bit reload value (RCAP2H:RCAP2L). The Timer 2 clock source is fixed at SYSCLK/2. The Timer 2 overflow rate can be calculated as follows: T2_OVERFLOWRATE = (SYSCLK/2) / (65536 – [RCAP2H:RCAP2L]). ...

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... Mode 1. Mode 3 operation transmits 11 bits: a start bit, 8 data bits (LSB first), a programmable ninth data bit, and a stop bit. Timer 1 or Timer 2 overflows generate the baud rate just as with Mode 1. In summary, Mode 3 transmits using the same protocol as Mode 2 but with Mode 1 baud rate generation. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 SMOD Mode 2 Baud Rate = 2 * (SYSCLK / 64). ...

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... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 18.2. Multiprocessor Communications Modes 2 and 3 support multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte in that its ninth bit is logic data byte, the ninth bit is always set to logic 0 ...

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... This is actually two registers; a transmit and a receive buffer register. When data is moved to SBUF, it goes to the transmit buffer and is held for serial transmission. Moving a byte to SBUF is what initiates the transmission. When data is moved from SBUF, it comes from the receive buffer. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Divide Factor Timer 1 Load Value* 208 0xF3 ...

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... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 18.9. SCON: Serial Port Control Register R/W R/W R/W SM0 SM1 SM2 Bit7 Bit6 Bit5 Bits7-6: SM0-SM1: Serial Port Operation Mode. These bits select the Serial Port Operation Mode. SM0 SM1 Mode 0 0 Mode 0: Synchronous Mode 0 1 Mode 1: 8-Bit UART, Variable Baud Rate ...

Page 138

... When C/T0 is set to logic 1, high-to-low transitions at the selected input pin increment the timer register. (Refer to Port I/O Section 15.1 for information on selecting and configuring external I/O pins.) C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Timer 2: 16-bit counter/timer with auto-reload 16-bit counter/timer with capture Baud rate generator Rev ...

Page 139

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD. the input signal /INT0 is logic-level one. Setting GATE0 to logic 1 allows the timer to be controlled by the external input signal /INT0, facilitating pulse width measurements. TR0 Don’t Care Setting TR0 does not reset the timer register ...

Page 140

... When in Mode 2, Timer 1 operates identically to Timer 0. Both counter/timers are enabled and configured in Mode 2 in the same manner as Mode 0. Figure 19.2. T0 Mode 2 Block Diagram CKCON SYSCLK 1 T0 Crossbar TR0 GATE0 /INT0 Crossbar C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 TMOD ...

Page 141

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 19.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) Timer 0 and Timer 1 behave differently in Mode 3. Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in TCON and TMOD: TR0, C/T0, GATE0 and TF0. It can use either the system clock or an external input signal as its timebase. The TH0 register is restricted to a timer function sourced by the system clock ...

Page 142

... Interrupt 0 service routine if IT0 = 1. This flag is the inverse of the /INT0 input signal’s logic level when IT0 = 0. Bit0: IT0: Interrupt 0 Type Select. This bit selects whether the configured /INT0 signal will detect falling edge or active-low level-sensitive interrupts. 0: /INT0 is level triggered. 1: /INT0 is edge triggered. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W TR0 IE1 IT1 Bit4 Bit3 Bit2 Rev ...

Page 143

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 19.5. TMOD: Timer Mode Register R/W R/W R/W GATE1 C/T1 T1M1 Bit7 Bit6 Bit5 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled only when TR1 = 1 AND /INT1 = logic level one. Bit6: C/T1: Counter/Timer 1 Select ...

Page 144

... T0M: Timer 0 Clock Select. This bit controls the division of the system clock supplied to Counter/Timer 0. 0: Counter/Timer uses the system clock divided by 12. 1: Counter/Timer uses the system clock. Bits2-0: Reserved. Read = 000b, Must Write = 000. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W T1M T0M ...

Page 145

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 19.7. TL0: Timer 0 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. Figure 19.8. TL1: Timer 1 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TL1: Timer 1 Low Byte ...

Page 146

... Timer 2 operating modes and the T2CON bits used to configure the counter/timer. Detailed descriptions of each mode follow. RCLK TCLK CP/RL2 C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 It operates in one of three modes: 16-bit TR2 Mode 1 1 16-bit Counter/Timer with Capture 0 1 16-bit Counter/Timer with Auto-Reload X 1 Baud Rate Generator for Baud Rate Generator for ...

Page 147

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 19.2.1. Mode 0: 16-bit Counter/Timer with Capture In this mode, Timer 2 operates as a 16-bit counter/timer with capture facility. A high-to-low transition on the T2EX input pin causes the 16-bit value in Timer 2 (TH2, TL2 loaded into the capture registers (RCAP2H, RCAP2L). Timer 2 can use either SYSCLK, SYSCLK divided by 12, or high-to-low transitions on the external T2 pin as its clock source when operating in Counter/Timer with Capture mode ...

Page 148

... C/T2 bit. If EXEN2 is set to logic 1, a high-to-low transition on T2EX will also cause Timer reloaded. If EXEN2 is cleared, transitions on T2EX will be ignored. Figure 19.12. T2 Mode 1 Block Diagram 12 0 SYSCLK Crossbar TR2 EXEN2 T2EX Crossbar C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 CKCON TL2 TH2 TCLK Reload RCAP2L RCAP2H Rev ...

Page 149

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 19.2.3. Mode 2: Baud Rate Generator Timer 2 can be used as a baud rate generator for the serial port (UART) when the UART is operated in modes (refer to Section 18.1 for more information on UART operational modes). In Baud Rate Generator mode, Timer 2 works similarly to the auto-reload mode. On overflow, the 16-bit value held in the two capture registers (RCAP2H, RCAP2L) is automatically loaded into the counter/timer register. However, the TF2 overflow flag is not set and no interrupt is generated. Instead, the overflow event is used as the input to the UART’ ...

Page 150

... T2EX to be recognized and used to trigger captures or reloads. If RCLK or TCLK is set, this bit is ignored and Timer 2 will function in auto-reload mode. 0: Auto-reload on Timer 2 overflow or high-to-low transition at T2EX (EXEN2 = 1). 1: Capture on high-to-low transition at T2EX (EXEN2 = 1). C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W TCLK EXEN2 ...

Page 151

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 19.15. RCAP2L: Timer 2 Capture Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: RCAP2L: Timer 2 Capture Register Low Byte. The RCAP2L register captures the low byte of Timer 2 when Timer 2 is configured in capture mode. When Timer 2 is configured in auto-reload mode, it holds the low byte of the reload value ...

Page 152

... T3M: Timer 3 Clock Select. This bit controls the division of the system clock supplied to Counter/Timer 3. 0: Counter/Timer 3 uses the system clock divided by 12. 1: Counter/Timer 3 uses the system clock. Bit0: UNUSED. Read = 0, Write = don’t care. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 TMR3L TMR3H TCLK Reload TMR3RLL TMR3RLH R/W ...

Page 153

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 19.21. TMR3RLL: Timer 3 Reload Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TMR3RLL: Timer 3 Reload Register Low Byte. Timer 3 is configured as an auto-reload timer. This register holds the low byte of the reload value. Figure 19.22. TMR3RLH: Timer 3 Reload Register High Byte ...

Page 154

... The PCA is configured and controlled through the system controller’s Special Function Registers. The basic PCA block diagram is shown in Figure 20.1. Figure 20.1. PCA Block Diagram 00 /12 System Clock Overflow CPS=11 Capture/Compare Capture/Compare Module 0 C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 16-Bit Counter/Timer Capture/Compare Capture/Compare Module 1 Module 2 Crossbar Port I/O Rev. 1.7 Capture/Compare Module 3 Module 4 154 ...

Page 155

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 20.1. Capture/Compare Modules Each module can be configured to operate independently in one of four operation modes: Edge-triggered Capture, Software Timer, High Speed Output, or Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the CIP-51 system controller. These registers are used to exchange data with a module and configure the module’ ...

Page 156

... CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software. Figure 20.3. PCA Capture Mode Diagram CEXn Port I/O Crossbar C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 PCA Interrupt PCA0CPMn PCA0CN ...

Page 157

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 20.1.2. Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer is compared to the module’s 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared by software ...

Page 158

... PCA0CPHn without software intervention good practice to write to PCA0CPHn instead of PCA0CPLn to avoid glitches in the digital comparator. Setting the ECOMn and PWMn bits in the PCA0CPMn register enables Pulse Width Modulator mode. Figure 20.6. PCA PWM Mode Diagram Write to PCA0CPLn 0 ENB Reset Write to PCA0CPHn ENB 1 C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 PCA0CPHn PCA0CPMn ...

Page 159

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 20.2. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). PCA0H at the same time. By reading the PCA0L Register first, this allows the PCA0H value to be held (at the time PCA0L was read) until the user reads the PCA0H Register ...

Page 160

... This bit is set by hardware when a match or capture occurs. When the CCF interrupt is enabled, setting this bit causes the CPU to vector to the CCF interrupt service routine. This bit is not automatically cleared by hardware and must be cleared by software. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W CCF4 ...

Page 161

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 20.9. PCA0MD: PCA Mode Register R/W R/W R/W CIDL - - Bit7 Bit6 Bit5 Bit7: CIDL: PCA Counter/Timer Idle Control. Specifies PCA behavior when CPU is in Idle Mode. 0: PCA continues to function normally while the system controller is in Idle Mode. 1: PCA operation is suspended while the system controller is in Idle Mode. ...

Page 162

... CEXn pin. 0: Disabled. 1: Enabled. Bit0: ECCFn: Capture/Compare Flag Interrupt Enable. This bit sets the masking of the Capture/Compare Flag (CCFn) interrupt. 0: Disable CCFn interrupts. 1: Enable a Capture/Compare Flag interrupt request when CCFn is set. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 R/W R/W R/W CAPNn MATn TOGn Bit4 Bit3 Bit2 Rev ...

Page 163

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 20.11. PCA0L: PCA Counter/Timer Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: PCA0L: PCA Counter/Timer Low Byte. The PCA0L register holds the low byte (LSB) of the 16-bit PCA Counter/Timer. Figure 20.12. PCA0H: PCA Counter/Timer High Byte ...

Page 164

... Flash Address Selects FLASHADR Register which holds the address of all Flash read, write, and erase operations 0x0085 Flash Scale Selects FLASHSCL Register which controls the prescaler used to generate timing signals for Flash operations C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Rev. 1.7 Reset Value 0x0004 Bit0 164 ...

Page 165

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 21.1. Boundary Scan The Data Register in the Boundary Scan path is an 87-bit shift register. The Boundary DR provides control and observability of all the device pins as well as the SFR bus and Weak Pullup feature via the EXTEST and SAMPLE commands. Table 21.1. Boundary Data Register Bit Definitions EXTEST provides access to both capture and update actions, while Sample only performs a capture ...

Page 166

... Figure 21.2. DEVICEID: JTAG Device ID Register Version Part Number Bit31 Bit28 Bit27 Version = 0000b (Revision 0001b (Revision B) Part Number = 0000 0000 0000 0000b or = 0000 0000 0000 0010b Manufacturer ID = 0010 0100 001b (Silicon Laboratories) C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Manufacturer ID Bit12 Bit11 Rev. 1.7 Reset Value 1 (Varies) Bit1 Bit0 166 ...

Page 167

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 21.2. Flash Programming Commands The Flash memory can be programmed directly over the JTAG interface using the Flash Control, Flash Data, Flash Address, and Flash Scale registers. These Indirect Data Registers are accessed via the JTAG Instruction Register. Read and write operations on indirect data registers are performed by first setting the appropriate DR address in the IR register ...

Page 168

... Figure 21.4. FLASHADR: JTAG Flash Address Register Bit15 This register holds the address for all JTAG Flash read, write, and erase operations. This register autoincrements after each read or write, regardless of whether the operation succeeded or failed. Bits15-0: Flash Operation 16-bit Address. C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 WRMD0 RDMD3 RDMD2 Bit4 Bit3 Bit2 Rev ...

Page 169

... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Figure 21.5. FLASHDAT: JTAG Flash Data Register DATA7 DATA6 DATA5 DATA4 Bit9 Bit8 Bit7 Bit6 This register is used to read or write data to the Flash memory across the JTAG interface. Bits9-2: DATA7-0: Flash Data Byte. Bit1: FAIL: Flash Fail Bit. 0: Previous Flash memory operation was successful. ...

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... The WDT is disabled when the MCU is halted during single stepping breakpoint. The C8051F000DK, C8051F005DK, C8051F010DK, and C8051F015DK are development kits with all the hardware and software necessary to develop application code and perform in-circuit debugging with each MCU in the C8051F000 family ...

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... C8051F000/1/2/5/6/7 C8051F010/1/2/5/6/7 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice ...

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