M38039FFLHP#U0 Renesas Electronics America, M38039FFLHP#U0 Datasheet
M38039FFLHP#U0
Specifications of M38039FFLHP#U0
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M38039FFLHP#U0 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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Group (Spec.L) SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 3803 group (Spec.L) is the 8-bit microcomputer based on the 740 family core technology. The 3803 group (Spec.L) is designed for household products, office automation equipment, and controlling systems that require ...
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Group (Spec. RDY3 CLK3 / / REF AV ...
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Group (Spec.L) PIN CONFIGURATION (TOP VIEW /AN 6 CLK3 / ...
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Group (Spec.L) Table 1 Performance overview Parameter Number of basic instructions Minimum instruction execution time Oscillation frequency Memory Mask ROM version sizes Flash memory version I/O port P0-P6 Software pull-up resistors Interrupt Timer Serial interface PWM A/D converter D/A ...
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Group (Spec.L) Fig 4. Functional block diagram Rev.1.01 Jan 25, 2008 Page 5 of 117 REJ03B0212-0101 ...
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Group (Spec.L) PIN DESCRIPTION Table 2 Pin description Pin Name Power source CC SS CNV CNV input Reference REF voltage AV Analog power SS source RESET Reset input X Main clock input • ...
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Group (Spec.L) PART NUMBERING Product name M3803 9 M Fig 5. Part numbering Rev.1.01 Jan 25, 2008 Page 7 of 117 REJ03B0212-0101 F L− XXX SP Package code SP : PRDP0064BA-A (64P4B PLQP0064KB-A (64P6Q- PLQP0064GA-A ...
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Group (Spec.L) GROUP EXPANSION Renesas plans to expand the 3803 group (Spec.L) as follows. Memory Size • Flash memory size .....................................................60 Kbytes • Mask ROM size .........................................................60 Kbytes • RAM size ................................................................. 2048 bytes Memory Expansion Plan ROM size ...
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Group (Spec.L) FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 3803 group (Spec.L) uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details ...
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Group (Spec.L) Interrupt request Push Return M(S)←( Address on Stack (S)←(S) − 1 M(S)←( ← − Subroutine Execute RTS (S)←( POP Return Address from Stack (PC ...
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Group (Spec.L) [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch operations can ...
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Group (Spec.L) [CPU Mode Register (CPUM)] 003B The CPU mode register contains the stack page selection bit, the internal system clock control bits, etc. The CPU mode register is allocated at address 003B b7 Fig 9. Structure of CPU ...
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Group (Spec.L) MISRG (1) Bit 0 of address 0010 : Oscillation stabilizing time 16 set after STP instruction released bit When the MCU stops the clock oscillation by the STP instruction and the STP instruction has been released by ...
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Group (Spec.L) MEMORY • Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. • RAM The RAM is used for data storage and for stack ...
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Group (Spec.L) Port P0 (P0) 0000 16 Port P0 direction register (P0D) 0001 16 Port P1 (P1) 0002 16 Port P1 direction register (P1D) 0003 16 Port P2 (P2) 0004 16 Port P2 direction register (P2D) 0005 16 Port ...
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Group (Spec.L) I/O PORTS The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input port ...
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Group (Spec.L) (1) Ports Pull-up control bit Direction register Port latch Data bus A/D converter input (3) Ports Pull-up control bit Direction register Data bus Port latch (5) Ports ...
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Group (Spec.L) (9) Port P3 7 Pull-up control bit Serial I/O3 mode selection bit Serial I/O3 enable bit S output enable bit RDY3 Direction register Data bus Port latch Serial I/O3 ready output (11) Port P4 1 Pull-up control ...
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Group (Spec.L) (15) Port P5 2 Pull-up control bit Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Direction register Data bus Port latch Serial I/O2 clock output Serial I/O2 external clock input (17) Ports P5 , ...
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Group (Spec. Fig 16. Structure of port pull-up control register (1) Rev.1.01 Jan 25, 2008 Page 20 of 117 REJ03B0212-0101 Port P0 pull-up control register (PULL0: address 0FF0 ) 16 P0 pull-up control bit 0 ...
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Group (Spec. Fig 17. Structure of port pull-up control register (2) Rev.1.01 Jan 25, 2008 Page 21 of 117 REJ03B0212-0101 Port P2 pull-up control register (PULL2: address 0FF2 ) 16 P2 pull-up control bit 0 ...
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Group (Spec. Fig 18. Structure of port pull-up control register (3) Rev.1.01 Jan 25, 2008 Page 22 of 117 REJ03B0212-0101 Port P4 pull-up control register (PULL4: address 0FF4 ) 16 P4 pull-up control bit 0 ...
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Group (Spec. Fig 19. Structure of port pull-up control register (4) Rev.1.01 Jan 25, 2008 Page 23 of 117 REJ03B0212-0101 Port P6 pull-up control register (PULL6: address 0FF6 ) 16 P6 pull-up control bit ...
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Group (Spec.L) Termination of unused pins • Termination of common pins I/O ports: Select an input port or an output port and follow each processing method. In addition recommended that related registers be overwritten periodically to prevent ...
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Group (Spec.L) INTERRUPTS The 3803 group (Spec.L) interrupts are vector interrupts with a fixed priority scheme, and generated by 16 sources among 21 sources: 8 external, 12 internal, and 1 software. The interrupt sources, vector addresses are shown in ...
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Group (Spec.L) Interrupt request bit Interrupt enable bit Interrupt disable flag (I) Fig 20. Interrupt control diagram • Interrupt Disable Flag The interrupt disable flag is assigned to bit 2 of the processor status register. This flag controls the ...
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Group (Spec. Interrupt edge selection register (INTEDGE : address 003A INT interrupt edge selection bit 0 INT interrupt edge selection bit 1 Not used (returns “0” when read) INT interrupt edge selection bit 2 INT interrupt edge ...
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Group (Spec.L) • Interrupt Request Generation, Acceptance, and Handling Interrupts have the following three phases. (i) Interrupt Request Generation An interrupt request is generated by an interrupt source (external interrupt signal input, timer underflow, etc.) and the corresponding request ...
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Group (Spec.L) Instruction cycle Internal clock φ SYNC Interrupt acceptance timing points IR1 IR2 : Timings points at which the interrupt request bit is set to “1”. Note : Period 2 indicates the last ...
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Group (Spec.L) TIMERS • 8-bit Timers The 3803 group (Spec.L) has four 8-bit timers: timer 1, timer 2, timer X, and timer Y. The timer 1 and timer 2 use one prescaler in common, and the timer X and ...
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Group (Spec.L) (4) Pulse Width Measurement Mode • Mode selection This mode can be selected by setting “11” to the timer X operating mode bits (bits 1 and 0) and the timer Y operating mode bits (bits 5 and ...
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Group (Spec. “00” (1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024) “11” Divider Count source selection bit “10” X CIN Main clock division ratio selection bits f(X ) CIN CNTR active 0 edge switch bit ...
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Group (Spec.L) b7 Fig 26. Structure of timer XY mode register Rev.1.01 Jan 25, 2008 Page 33 of 117 REJ03B0212-0101 b0 Timer XY mode register (TM : address 0023 ) 16 Timer X operating mode bits ...
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Group (Spec. Fig 27. Structure of timer 12, X and timer Y, Z count source selection registers Rev.1.01 Jan 25, 2008 Page 34 of 117 REJ03B0212-0101 b0 Timer 12, X count source selection register (T12XCSS : address ...
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Group (Spec.L) • 16-bit Timer The timer 16-bit timer. When the timer reaches “0000 ...
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Group (Spec.L) (4) Pulse period measurement mode • Mode selection This mode can be selected by setting “010” to the timer Z operating mode bits (bits and setting “0” to the timer/event counter mode switch bit ...
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Group (Spec.L) (6) Programmable waveform generating mode • Mode selection This mode can be selected by setting “100” to the timer Z operating mode bits (bits and setting “0” to the timer/event counter mode switch bit ...
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Group (Spec.L) P4 /INT 2 1 Programmable one-shot generating mode Output level latch “001 ” “100 ” “101 Timer Z ” operating mode bits Port P4 latch Port P4 7 direction register Pulse period measurement mode ...
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Group (Spec. Note 1: When selecting the modes except the timer/event counter mode, set “0” to this bit. Fig 29. Structure of timer Z mode register Rev.1.01 Jan 25, 2008 Page 39 of 117 REJ03B0212-0101 Timer Z ...
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Group (Spec.L) FFFF 16 TL 0000 16 Fig 30. Timing chart of timer/event counter mode FFFF TL 0000 Waveform output from CNTR pin 2 Fig 31. Timing chart of pulse output mode Rev.1.01 Jan 25, 2008 Page 40 of ...
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Group (Spec.L) 0000 FFFF 16 Signal input from CNTR pin 2 Fig 32. Timing chart of pulse period measurement mode (Measuring term between two rising edges) 0000 FFFF 16 Signal input ...
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Group (Spec.L) FFFF 0000 Signal output from CNTR pin 2 Fig 34. Timing chart of programmable waveform generating mode FFFF Signal input from INT pin 1 Signal output from CNTR pin 2 Fig 35. Timing chart of programmable one-shot ...
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Group (Spec.L) SERIAL INTERFACE • Serial I/O1 Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation ...
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Group (Spec.L) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to “0”. Eight serial data transfer formats ...
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Group (Spec.L) [Transmit Buffer Register 1/Receive Buffer Register 1 (TB1/RB1)] 0018 16 The transmit buffer register 1 and the receive buffer register 1 are located at the same address. The transmit buffer is write-only and the receive buffer is ...
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Group (Spec.L) Serial I/O1 status register b7 b0 (SIO1STS : address 0019 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) ...
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Group (Spec.L) <Notes concerning serial I/O1> 1. Notes when selecting clock synchronous serial I/O 1.1 Stop of transmission operation • Note Clear the serial I/O1 enable bit and the transmit enable bit to “0” (serial I/O and transmit disabled). ...
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Group (Spec. output of reception side RDY1 • Note When signals are output from the S RDY1 side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, ...
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Group (Spec.L) • Serial I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2, the transmitter and the receiver must use the same clock. If the internal clock is used, ...
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Group (Spec.L) (1) Transfer clock Serial I/O2 register write signal Serial I/O2 output S OUT2 Serial I/O2 input S IN2 Receive enable signal S RDY2 Notes1: When the internal clock is selected as the transfer clock, the divide ratio ...
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Group (Spec.L) • Serial I/O3 Serial I/O3 can be used as either clock synchronous or asynchronous (UART) serial I/O3. A dedicated timer is also provided for baud rate generation CLK3 ...
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Group (Spec.L) (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O3 mode selection bit (b6) of the serial I/O3 control register to “0”. Eight serial data transfer formats ...
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Group (Spec.L) [Transmit Buffer Register 3/Receive Buffer Register 3 (TB3/RB3)] 0030 16 The transmit buffer register 3 and the receive buffer register 3 are located at the same address. The transmit buffer is write-only and the receive buffer is ...
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Group (Spec.L) Serial I/O3 status register b7 b0 (SIO3STS : address 0031 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) ...
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Group (Spec.L) <Notes concerning serial I/O3> 1. Notes when selecting clock synchronous serial I/O 1.1 Stop of transmission operation • Note Clear the serial I/O3 enable bit and the transmit enable bit to “0” (serial I/O and transmit disabled). ...
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Group (Spec. output of reception side RDY3 • Note When signals are output from the S RDY3 side by using an external clock in the clock synchronous serial I/O mode, set all of the receive enable bit, ...
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Group (Spec.L) PULSE WIDTH MODULATION (PWM) The 3803 group (Spec.H QzROM version) has PWM functions with an 8-bit resolution, based on a signal that is the clock input X or that clock input divided the clock ...
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Group (Spec.L) b7 Fig 51. Structure of PWM control register PWM output PWM register write signal PWM prescaler write signal When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the ...
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Group (Spec.L) A/D CONVERTER (successive approximation type) [AD Conversion Register 1, 2 (AD1, AD2)] 0035 0038 16 The AD conversion register is a read-only register that stores the result of an A/D conversion. When reading this register during an ...
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Group (Spec.L) b7 AD/DA control register (Address 0034 ) Comparator ...
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Group (Spec.L) D/A CONVERTER The 3803 group (Spec.L) has two internal D/A converters (DA and DA ) with 8-bit resolution. 2 The D/A conversion is performed by setting the value in each DA conversion register. The result of D/A ...
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Group (Spec.L) WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit ...
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Group (Spec.L) RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L” level for 16 cycles or more Then the RESET pin is IN returned to an “H” level (the power source ...
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Group (Spec.L) (1) Port P0 (P0) (2) Port P0 direction register (P0D) (3) Port P1 (P1) (4) Port P1 direction register (P1D) (5) Port P2 (P2) (6) Port P2 direction register (P2D) (7) Port P3 (P3) (8) Port P3 ...
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Group (Spec.L) CLOCK GENERATING CIRCUIT The 3803 group (Spec.L) has two built-in oscillation circuits: main clock X -X oscillation circuit and sub clock X IN OUT X oscillation circuit. An oscillation circuit can be formed by COUT connecting a ...
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Group (Spec. CIN COUT CIN COUT Note 1 : Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the ...
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Group (Spec. COUT CIN “0” “1” Port X C switch bit OUT Main clock division ratio selection bits (4) Low-speed mode High-speed or middle-speed mode Main clock stop bit Q S STP R instruction ...
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Group (Spec.L) Reset Middle-speed mode CM (f(φ MHz) “1”←→”0” MHz oscillating (32 kHz stopped) 4 Middle-speed mode CM (f(φ MHz) “1”←→”0” ...
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Group (Spec.L) FLASH MEMORY MODE The 3803 group (Spec.L)’s flash memory version has the flash memory that can be rewritten with a single power source. For this flash memory, three flash memory modes are available in which to read, ...
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Group (Spec.L) Boot Mode The control program for CPU rewrite mode must be written into the User ROM or Boot ROM area in parallel I/O mode beforehand. (If the control program is written into the Boot ROM area, the ...
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Group (Spec.L) Outline Performance CPU rewrite mode is usable in the single-chip or Boot mode. The only User ROM area can be rewritten. In CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed ...
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Group (Spec. Flash memory control register 2 (FMCR2: address : 0FE2 Not used Not used (do not write “1” to this bit.) Not used All user block E/W enable bit 0 : E/W disabled 1 : E/W ...
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Group (Spec.L) <Notes on CPU Rewrite Mode> Take the notes described below when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the system clock φ to 4.0 MHz or less using ...
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Group (Spec.L) Software Commands Table 12 lists the software commands. After setting the CPU rewrite mode select bit to “1”, execute a software command to specify an erase or program operation. Each software command is explained below. • Read ...
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Group (Spec.L) • Block Erase Command (20 / writing the command code “20 ” in the first bus cycle and 16 the confirmation command code “D0 16 the second bus cycle that follows, the block erase (erase ...
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Group (Spec.L) • Status Register The status register shows the operating status of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways: (1) By reading an ...
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Group (Spec.L) Full Status Check By performing full status check possible to know the execution results of erase and program operations. Figure 74 shows a full status check flowchart and the action to be taken when each ...
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Group (Spec.L) Functions To Inhibit Rewriting Flash Memory Version To prevent the contents of internal flash memory from being read out or rewritten easily, this MCU incorporates a ROM code protect function for use in parallel I/O mode and ...
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Group (Spec.L) • ID Code Check Function Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the programmer is compared with the ID code written ...
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Group (Spec.L) Parallel I/O Mode The parallel I/O mode is used to input/output software commands, address and data in parallel for operation (read, program and erase) to internal flash memory. Use the external device (writer) only for 3803 group ...
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Group (Spec.L) Standard serial I/O Mode The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is clock synchronized serial. This mode ...
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Group (Spec.L) Table 14 Description of pin function (Flash Memory Serial I/O Mode 1) Pin name Signal name V ,V Power supply CC SS CNV CNV SS SS Reset input RESET X Clock input IN X Clock output OUT ...
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Group (Spec. RDY3 CLK3 / /DA ...
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Group (Spec. RDY3 CLK3 / /DA ...
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Group (Spec. BUSY S CLK CNV SS RESET * Connect oscillation circuit. indicates flash memory pin. Fig 79. Connection for standard serial I/O mode 1 (M38039FFLSP) Rev.1.01 Jan ...
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Group (Spec. BUSY “L” input CNV SS RESET Connect oscillation circuit. indicates flash memory pin. Fig 80. Connection for standard serial I/O mode 2 (M38039FFLSP) Rev.1.01 Jan 25, ...
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Group (Spec.L) PIN CONFIGURATION (TOP VIEW /AN 6 CLK3 / ...
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Group (Spec.L) PIN CONFIGURATION (TOP VIEW /AN 6 CLK3 / ...
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Group (Spec.L) Power source RESET CNV CLK P4 (BUSY Limits Symbol Min. Typ. − td(CNV -RESET td(P4 -RESET Fig ...
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Group (Spec.L) T_VDD T_VPP T_RXD T_TXD T_SCLK T_PGM/OE/MD T_BUSY RESET circuit T_RESET GND Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF. Fig 85. When using programmer (in standard serial I/O ...
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Group (Spec. Open-collector buffer 1 Note : For the programming circuit, the wiring capacity of each signal pin must not ...
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Group (Spec.L) NOTES NOTES ON PROGRAMMING 1. Processor Status Register (1) Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular essential to initialize the T and D flags ...
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Group (Spec.L) Countermeasures against noise (1) Shortest wiring length 1. Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and ...
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Group (Spec.L) (3) Oscillator concerns In order to obtain the stabilized operation clock on the user system and its condition, contact the oscillator manufacturer and select the oscillator and oscillation circuit constants. Be careful espe-cially when range of votage ...
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Group (Spec.L) NOTES ON PERIPHERAL FUNCTIONS Notes on Input and Output Ports 1. Notes in standby state *1 In standby state for low-power dissipation, do not make input levels of an I/O port “undefined”. Even when an I/O port ...
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Group (Spec.L) Notes on Interrupts 1. Change of relevant register settings When the setting of the following registers or bits is changed, the interrupt request bit may be set to “1”. When not requiring the interrupt occurrence synchronized with ...
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Group (Spec.L) Notes on 8-bit Timer (timer • value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). • When switching the count source by ...
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Group (Spec.L) Notes on Serial Interface 1. Notes when selecting clock synchronous serial I/O (1) Stop of transmission operation As for serial I/ that can be used as either a clock synchronous or an asynchronous ...
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Group (Spec.L) Notes on PWM The PWM starts from “H” level after the PWM enable bit is set to enable and “L” level is temporarily output from the PWM pin. The length of this “L” level output is as ...
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Group (Spec.L) Notes on Restarting Oscillation • Restarting oscillation Usually, when the MCU stops the clock oscillation by STP instruction and the STP instruction has been released by an external interrupt source, the fixed values of Timer 1 and ...
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Group (Spec.L) Notes on Handling of Power Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (V pin) and GND pin ( source ...
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Group (Spec.L) ELECTRICAL CHARACTERISTICS Absolute maximum ratings Table 16 Absolute maximum ratings Symbol Parameter V Power source voltages CC V Input voltage Input voltage ...
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Group (Spec.L) Mask ROM Version Recommended operating conditions Table 17 Recommended operating conditions (1) (Mask ROM version 1 Symbol Parameter V Power source When start oscillating CC (1) voltage High-speed mode ...
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Group (Spec.L) Flash Memory Version Table 18 Recommended operating conditions (2) (Flash memory version 2 Symbol Parameter V Power source When start oscillating CC (1) voltage High-speed mode f( φ ) ...
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Group (Spec.L) Table 19 Recommended operating conditions (3) (Mask ROM version (Flash memory version: V Symbol Σ I “H” total peak output current OH(peak) Σ I “H” total peak output current OH(peak) Σ I “L” total peak ...
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Group (Spec.L) Electrical characteristics Table 20 Electrical characteristics (1) (Mask ROM version (Flash memory version: V Symbol Parameter V (1) “H” output voltage ...
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Group (Spec.L) Mask ROM Version Table 21 Electrical characteristics (2) (Mask ROM version 1 – °C, f(X CC Output transistors “off”, AD converter not operated) Symbol Parameter I Power source ...
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Group (Spec.L) Flash Memory Version Table 22 Electrical characteristics (3) (Flash memory version 2 – °C, f(X CC Output transistors “off”, AD converter not operated) Symbol Parameter I Power source ...
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Group (Spec.L) Mask ROM Version A/D converter characteristics Table 23 A/D converter recommended operating conditions (Mask ROM version 2 Symbol Parameter V Power source voltage CC (When A/D converter is used) ...
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Group (Spec.L) A/D converter characteristics Table 26 A/D converter recommended operating conditions (Flash memory version 2 Symbol Parameter V Power source voltage CC (When A/D converter is used) V Analog convert ...
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Group (Spec.L) Timing requirements and switching characteristics Table 30 Timing requirements (1) (Mask ROM version (Flash memory version: V Symbol Reset input “L” pulse width t (RESET Main clock ...
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Group (Spec.L) Table 31 Timing requirements (2) (Mask ROM version (Flash memory version: V Symbol Serial I/O1, serial I/O3 C CLK1 clock input cycle time C CLK3 Serial ...
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Group (Spec.L) Table 32 Switching characteristics (1) (Mask ROM version (Flash memory version: V Symbol Parameter Serial I/O1, serial I/O3 WH CLK1 clock output “H” pulse WH CLK3 width t (S ...
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Group (Spec.L) Table 33 Switching characteristics (2) (Mask ROM version (Flash memory version: V Symbol Parameter Serial I/O2 f CLK2 fall time of clock output t (CMOS) CMOS r (1) rise time of output ...
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Group (Spec.L) Single-chip mode timing diagram CNTR , CNTR 0 1 CNTR 2 INT , INT , INT INT , INT 00 40 INT , INT 01 41 RESET CIN S CLK1 S ...
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Group (Spec.L) PACKAGE OUTLINE Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of the Renesas Technology website. JEITA Package Code RENESAS Code P-SDIP64-17x56.4-1.78 PRDP0064BA SEATING PLANE e JEITA ...
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Group (Spec.L) JEITA Package Code RENESAS Code P-LQFP64-14x14-0.80 PLQP0064GA Index mark y e JEITA Package Code RENESAS Code P-TFLGA64-6x6-0.65 PTLG0064JA Rev.1.01 Jan 25, 2008 Page 117 ...
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REVISION HISTORY REVISION HISTORY Rev. Date Page 1.00 Apr.2, 2007 - 1.01 Jan.25, 2008 110 3803 Group (Spec.L) Data Sheet Description First edition issued The title “Power source circuit timing characteristics (Flash memory version)” is added and the value “2 ...
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Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained ...