MC68HC11E1CFNE3 Freescale Semiconductor, MC68HC11E1CFNE3 Datasheet - Page 145

IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E1CFNE3

Manufacturer Part Number
MC68HC11E1CFNE3
Description
IC MCU 8BIT 3MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11E1CFNE3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Controller Family/series
68HC11
No. Of I/o's
38
Eeprom Memory Size
512Byte
Ram Memory Size
512Byte
Cpu Speed
3MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Program Memory Size
512 B
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
22
Number Of Timers
8
Operating Supply Voltage
3 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

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9.7.1 Pulse Accumulator Control Register
Four of this register’s bits control an 8-bit pulse accumulator system. Another bit enables either the OC5
function or the IC4 function, while two other bits select the rate for the real-time interrupt system.
DDRA7 — Data Direction for Port A Bit 7
PAEN — Pulse Accumulator System Enable Bit
PAMOD — Pulse Accumulator Mode Bit
PEDGE — Pulse Accumulator Edge Control Bit
DDRA3 — Data Direction for Port A Bit 3
I4/O5 — Input Capture 4/Output Compare 5 Bit
RTR[1:0] — RTI Interrupt Rate Select Bits
Freescale Semiconductor
Refer to
This bit has different meanings depending on the state of the PAMOD bit, as shown in
Refer to
Refer to
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
0 = Event counter
1 = Gated time accumulation
0 = Output compare 5 function enable (no IC4)
1 = Input capture 4 function enable (no OC5)
Chapter 6 Parallel Input/Output (I/O)
Chapter 6 Parallel Input/Output (I/O)
9.5 Real-Time Interrupt
Address:
Reset:
Read:
Write:
Figure 9-25. Pulse Accumulator Control Register (PACTL)
DDRA7
$1026
PAMOD
Bit 7
0
0
0
1
1
Table 9-7. Pulse Accumulator Edge Control
PAEN
6
0
PEDGE
M68HC11E Family Data Sheet, Rev. 5.1
(RTI).
0
1
0
1
PAMOD
5
0
PAI falling edge increments the counter.
PAI rising edge increments the counter.
A 0 on PAI inhibits counting.
A 1 on PAI inhibits counting.
PEDGE
Ports.
Ports.
4
0
Action on Clock
DDRA3
3
0
I4/O5
2
0
RTR1
1
0
RTR0
Bit 0
Pulse Accumulator
0
Table
9-7.
145

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