MC68HC11E1CFNE3 Freescale Semiconductor, MC68HC11E1CFNE3 Datasheet - Page 98

IC MCU 8BIT 3MHZ 52-PLCC

MC68HC11E1CFNE3

Manufacturer Part Number
MC68HC11E1CFNE3
Description
IC MCU 8BIT 3MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC11E1CFNE3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Controller Family/series
68HC11
No. Of I/o's
38
Eeprom Memory Size
512Byte
Ram Memory Size
512Byte
Cpu Speed
3MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Program Memory Size
512 B
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
22
Number Of Timers
8
Operating Supply Voltage
3 V to 5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

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6.2 Port A
Port A shares functions with the timer system and has:
DDRA7 — Data Direction for Port A Bit 7
PAEN — Pulse Accumulator System Enable Bit
PAMOD — Pulse Accumulator Mode Bit
PEDGE — Pulse Accumulator Edge Control Bit
DDRA3 — Data Direction for Port A Bit 3
I4/O5 — Input Capture 4/Output Compare 5 Bit
RTR[1:0] — RTI Interrupt Rate Select Bits
98
Parallel Input/Output (I/O) Ports
Overridden if an output compare function is configured to control the PA7 pin
The pulse accumulator uses port A bit 7 as the PAI input, but the pin can also be used as
general-purpose I/O or as an output compare.
Refer to
Refer to
Refer to
This bit is overridden if an output compare function is configured to control the PA3 pin.
Refer to
Refer to
0 = Input
1 = Output
0 = Input
1 = Output
Three input-only pins
Three output-only pins
Two bidirectional I/O pins
Alternate function:
Chapter 9 Timing
Chapter 9 Timing
Chapter 9 Timing
Chapter 9 Timing
Chapter 9 Timing
Even when port A bit 7 is configured as an output, the pin still drives the
input to the pulse accumulator.
Address:
Address:
And/or:
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 6-2. Pulse Accumulator Control Register (PACTL)
I = Indeterminate after reset
DDRA7
$1000
$1026
OC1
Bit 7
PA7
Bit 7
PAI
0
I
Systems.
Systems.
Systems.
Systems.
Systems.
Figure 6-1. Port A Data Register (PORTA)
PAEWN
M68HC11E Family Data Sheet, Rev. 5.1
OC2
OC1
PA6
6
0
6
0
PAMOD
OC3
OC1
PA5
5
0
5
0
NOTE
PEDGE
OC4
OC1
PA4
4
0
4
0
IC4/OC5
DDRA3
OC1
PA3
3
3
0
I
I4/O5
PA2
IC1
2
2
0
I
RTR1
PA1
IC2
1
1
0
I
Freescale Semiconductor
RTR0
Bit 0
PA0
Bit 0
IC3
0
I

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