C8051F022-GQR Silicon Laboratories Inc, C8051F022-GQR Datasheet - Page 145

• Manufacturer Part Number: C8051F022-GQR
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F02xr

Specifications of C8051F022-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: 336-1200 - DEV KIT FOR F020/F021/F022/F023
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.
The C8051F020/1/2/3 MCUs include 4k bytes of on-chip RAM mapped into the external data memory space
(XRAM), as well as an External Data Memory Interface which can be used to access off-chip memories and memory-
mapped devices connected to the GPIO ports. The external memory space may be accessed using the external move
instruction (MOVX) and the data pointer (DPTR), or using the MOVX indirect addressing mode using R0 or R1. If
the MOVX instruction is used with an 8-bit address operand (such as @R1), then the high byte of the 16-bit address
is provided by the External Memory Interface Control Register (EMI0CN, shown in Figure 16.1). Note: the MOVX
instruction can also be used for writing to the FLASH memory. See
for details. The MOVX instruction accesses XRAM by default. The EMIF can be configured to appear on the lower
I/O ports (P0-P3) or the upper I/O ports (P4-P7).
16.1. Accessing XRAM
The XRAM memory space is accessed using the MOVX instruction. The MOVX instruction has two forms, both of
which use an indirect addressing method. The first method uses the Data Pointer, DPTR, a 16-bit register which con-
tains the effective address of the XRAM location to be read or written. The second method uses R0 or R1 in combina-
tion with the EMI0CN register to generate the effective XRAM address. Examples of both of these methods are given
below.
16.1.1. 16-Bit MOVX Example
The 16-bit form of the MOVX instruction accesses the memory location pointed to by the contents of the DPTR reg-
ister. The following series of instructions reads the value of the byte at address 0x1234 into the accumulator A:

The above example uses the 16-bit immediate MOV instruction to set the contents of DPTR. Alternately, the DPTR
can be accessed through the SFR registers DPH, which contains the upper 8-bits of DPTR, and DPL, which contains
the lower 8-bits of DPTR.
16.1.2. 8-Bit MOVX Example
The 8-bit form of the MOVX instruction uses the contents of the EMI0CN SFR to determine the upper 8-bits of the
effective address to be accessed and the contents of R0 or R1 to determine the lower 8-bits of the effective address to
be accessed. The following series of instructions read the contents of the byte at address 0x1234 into the accumulator
A.
EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM
MOV
MOVX
MOV
MOV
MOVX
DPTR, #1234h
A, @DPTR
EMI0CN, #12h
R0, #34h
a, @R0
; load DPTR with 16-bit address to read (0x1234)
; load contents of 0x1234 into accumulator A
; load high byte of address into EMI0CN
; load low byte of address into R0 (or R1)
; load contents of 0x1234 into accumulator A
Rev. 1.4
Section “15. FLASH MEMORY” on page 139
C8051F020/1/2/3
145