MC68HC11E1VFNE3 Freescale Semiconductor, MC68HC11E1VFNE3 Datasheet - Page 96

MCU 8-BIT 512 RAM 3MHZ 52-PLCC

MC68HC11E1VFNE3

Manufacturer Part Number
MC68HC11E1VFNE3
Description
MCU 8-BIT 512 RAM 3MHZ 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC11E1VFNE3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Type
ROMless
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
52-PLCC
Processor Series
HC11E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC11E1VFNE3
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Resets and Interrupts
masked), the MCU starts up, beginning with the stacking sequence leading to normal service of the XIRQ
request. If X is set to 1 (XIRQ masked or inhibited), then processing continues with the instruction that
immediately follows the STOP instruction, and no XIRQ interrupt service is requested or pending.
Because the oscillator is stopped in stop mode, a restart delay may be imposed to allow oscillator
stabilization upon leaving stop. If the internal oscillator is being used, this delay is required; however, if a
stable external oscillator is being used, the DLY control bit can be used to bypass this startup delay. The
DLY control bit is set by reset and can be optionally cleared during initialization. If the DLY equal to 0
option is used to avoid startup delay on recovery from stop, then reset should not be used as the means
of recovering from stop, as this causes DLY to be set again by reset, imposing the restart delay. This same
delay also applies to power-on reset, regardless of the state of the DLY control bit, but does not apply to
a reset while the clocks are running.
M68HC11E Family Data Sheet, Rev. 5.1
96
Freescale Semiconductor

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