R4F24268NVFQV Renesas Electronics America, R4F24268NVFQV Datasheet
R4F24268NVFQV
Specifications of R4F24268NVFQV
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R4F24268NVFQV Summary of contents
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The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2426, H8S/2426R, H8S/2424 Group 16 Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2400 Series All information contained in these ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU intended for users designing application systems incorporating the MCU. A basic knowledge ...
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Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this ...
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Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described ...
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Description of Abbreviations The abbreviations used in this manual are listed below. • Abbreviations specific to this product Abbreviation Description BSC Bus controller CPG Clock pulse generator INT Interrupt controller SCI Serial communication interface TMR 8-bit timer TPU 16-bit ...
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Section 1 Overview................................................................................................1 1.1 Features.................................................................................................................................. 1 1.1.1 Applications.............................................................................................................. 1 1.1.2 Overview of Specifications....................................................................................... 2 1.2 List of Products...................................................................................................................... 9 1.3 Block Diagrams ................................................................................................................... 14 1.4 Pin Description .................................................................................................................... 16 1.4.1 Pin Assignments ..................................................................................................... 16 1.4.2 Pin Assignments in Each Operating ...
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Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)................. 75 2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn..... 75 2.7.5 Absolute Address—@aa:8/@aa:16/@aa:24/@aa:32.............................................. 75 2.7.6 Immediate—#xx:8/#xx:16/#xx:32.......................................................................... 76 2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) ...................................... 76 2.7.8 Memory Indirect—@@aa:8 ................................................................................... ...
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Section 5 Interrupt Controller ............................................................................107 5.1 Features.............................................................................................................................. 107 5.2 Input/Output Pins............................................................................................................... 109 5.3 Register Descriptions ......................................................................................................... 110 5.3.1 Interrupt Control Register (INTCR) ..................................................................... 111 5.3.2 Interrupt Priority Registers (IPRA to IPRN)............................................. 112 5.3.3 IRQ Enable Register (IER) ...
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Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL) .............................. 167 6.3.7 Bus Control Register (BCR) ................................................................................. 168 6.3.8 Address/Data Multiplexed I/O Control Register (MPXCR) ................................. 170 6.3.9 DRAM Control Register (DRAMCR) ...
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Byte Access Control ............................................................................................. 234 6.7.11 Burst Operation..................................................................................................... 236 6.7.12 Refresh Control..................................................................................................... 241 6.7.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface..... 247 6.8 Synchronous DRAM Interface........................................................................................... 250 6.8.1 Setting Continuous Synchronous DRAM Space................................................... 250 6.8.2 Address ...
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External Bus Release Function and CBR Refreshing/Auto Refreshing................ 312 6.15.4 BREQO Output Timing ........................................................................................ 313 6.15.5 Notes on Usage of the Synchronous DRAM ........................................................ 313 Section 7 DMA Controller (DMAC)................................................................. 315 7.1 Features.............................................................................................................................. 315 7.2 Input/Output Pins............................................................................................................... 317 7.3 ...
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Section 8 EXDMA Controller (EXDMAC) ......................................................407 8.1 Features.............................................................................................................................. 407 8.2 Input/Output Pins............................................................................................................... 409 8.3 Register Descriptions ......................................................................................................... 410 8.3.1 EXDMA Source Address Register (EDSAR)....................................................... 410 8.3.2 EXDMA Destination Address Register (EDDAR)............................................... 411 8.3.3 EXDMA Transfer Count Register (EDTCR)........................................................ 411 8.3.4 ...
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Location of Register Information and DTC Vector Table ................................................. 485 9.5 Operation ........................................................................................................................... 489 9.5.1 Normal Mode........................................................................................................ 492 9.5.2 Repeat Mode......................................................................................................... 493 9.5.3 Block Transfer Mode ............................................................................................ 494 9.5.4 Chain Transfer ...................................................................................................... 495 9.5.5 Interrupt Sources................................................................................................... 496 9.5.6 Operation ...
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Port 3 Register (PORT3)....................................................................................... 569 10.3.4 Port 3 Open Drain Control Register (P3ODR) ..................................................... 570 10.3.5 Pin Functions ........................................................................................................ 571 10.4 Port 4.................................................................................................................................. 574 10.4.1 Port 4 Register (PORT4)....................................................................................... 574 10.4.2 Pin Functions ........................................................................................................ 574 10.5 Port 5.................................................................................................................................. 576 ...
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Port B Open Drain Control Register (PBODR) .................................................... 624 10.10.6 Pin Functions ........................................................................................................ 625 10.10.7 Port B Input Pull-Up MOS States......................................................................... 633 10.11 Port C ................................................................................................................................. 634 10.11.1 Port C Data Direction Register (PCDDR) ............................................................ 634 10.11.2 Port C ...
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Port H................................................................................................................................. 681 10.16.1 Port H Data Direction Register (PHDDR)............................................................ 681 10.16.2 Port H Data Register (PHDR)............................................................................... 683 10.16.3 Port H Register (PORTH)..................................................................................... 683 10.16.4 Port H Open Drain Control Register (PHODR).................................................... 684 10.16.5 Pin Functions ........................................................................................................ 685 10.17 ...
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PWM Modes......................................................................................................... 765 11.4.6 Phase Counting Mode........................................................................................... 771 11.5 Interrupt Sources................................................................................................................ 779 11.6 DTC Activation.................................................................................................................. 783 11.7 DMAC Activation.............................................................................................................. 783 11.8 A/D Converter Activation.................................................................................................. 783 11.9 Operation Timing............................................................................................................... 784 11.9.1 Input/Output Timing ............................................................................................. 784 11.9.2 Interrupt Signal Timing ........................................................................................ ...
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Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) .................. 822 12.4.7 Inverted Pulse Output ........................................................................................... 824 12.4.8 Pulse Output Triggered by Input Capture ............................................................. 825 12.5 Usage Notes ....................................................................................................................... 826 12.5.1 Module Stop Function Setting .............................................................................. ...
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Mode Setting with Cascaded Connection ............................................................. 851 13.8.7 Module Stop Function Setting .............................................................................. 851 13.8.8 Interrupts in Module Stop State ............................................................................ 851 Section 14 Watchdog Timer (WDT) ................................................................. 853 14.1 Features.............................................................................................................................. 853 14.2 Input/Output Pin ................................................................................................................ 854 14.3 Register ...
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Receive Data Sampling Timing and Reception Margin in Asynchronous Mode......................................................................................... 902 15.4.3 Clock..................................................................................................................... 903 15.4.4 SCI Initialization (Asynchronous Mode).............................................................. 904 15.4.5 Data Transmission (Asynchronous Mode) ........................................................... 905 15.4.6 Serial Data Reception (Asynchronous Mode) ...................................................... 907 15.5 Multiprocessor Communication Function.......................................................................... ...
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Section Bus Interface 2 (IIC2)................................................................ 955 16.1 Features.............................................................................................................................. 955 16.2 Input/Output Pins............................................................................................................... 957 16.3 Register Descriptions ......................................................................................................... 958 2 16.3 Bus Control Register A (ICCRA) ................................................................... 960 2 16.3 Bus Control Register ...
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Interrupt Source ............................................................................................................... 1017 17.6 A/D Conversion Accuracy Definitions ............................................................................ 1018 17.7 Usage Notes ..................................................................................................................... 1020 17.7.1 Module Stop Function Setting ............................................................................ 1020 17.7.2 A/D Input Hold Function in Software Standby Mode ........................................ 1020 17.7.3 Restarting the A/D Converter ...
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Relationship between Data Input/Output Pins and Shift Register ...................... 1053 19.4.4 Communication Modes and Pin Functions ......................................................... 1054 19.4.5 SSU Mode........................................................................................................... 1056 19.4.6 SCS Pin Control and Conflict Error.................................................................... 1067 19.4.7 Clock Synchronous Communication Mode ........................................................ 1068 19.5 Interrupt ...
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Serial Communication Interface Specification for Boot Mode........................................ 1102 21.11 Programmer Mode ........................................................................................................... 1132 Section 22 Clock Pulse Generator ...................................................................1133 22.1 Register Descriptions ....................................................................................................... 1134 22.1.1 System Clock Control Register (SCKCR) .......................................................... 1134 22.1.2 PLL Control Register (PLLCR).......................................................................... 1136 22.2 ...
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Section 24 List of Registers............................................................................. 1165 24.1 Register Addresses (Address Order)................................................................................ 1166 24.2 Register Bits..................................................................................................................... 1181 24.3 Register States in Each Operating Mode ......................................................................... 1201 Section 25 Electrical Characteristics ...............................................................1217 25.1 Electrical Characteristics for H8S/2426 Group and H8S/2426R Group (3-V ...
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Flash Memory Characteristics ............................................................................ 1312 25.6 Timing Charts (5-V Version)........................................................................................... 1314 25.6.1 Clock Timing ...................................................................................................... 1314 25.6.2 Control Signal Timing ........................................................................................ 1316 25.6.3 Bus Timing ......................................................................................................... 1317 25.6.4 DMAC and EXDMAC Timing........................................................................... 1325 25.6.5 Timing of On-Chip Peripheral Modules ...
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H8S/2426, H8S/2426R, H8S/2424 Group 1.1 Features The H8S/2426 Group, H8S/2426R Group, and H8S/2424 Group are CISC (Complex Instruction Set Computer) microprocessors that integrate an H8S/2600 CPU core, which has an internal 16-bit architecture and is upward-compatible with Renesas-original H8/300, H8/300H, ...
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Section 1 Overview 1.1.2 Overview of Specifications The specifications of this LSI are summarized in table 1.1. Table 1.1 Overview of Specifications Module/ Type Function Description • Memory ROM • RAM RAM size: 64 Kbytes and 48 Kbytes • CPU ...
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H8S/2426, H8S/2426R, H8S/2424 Group Module/ Type Function Description • CPU MCU operating mode • • • • • • Interrupts Interrupt (sources) controller • • • • • DMA DMA controller • (DMAC) • • • REJ09B0466-0350 Rev. 3.50 Jul ...
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Section 1 Overview Module/ Type Function Description • DMA EXDMA controller • (EXDMAC) • • • • Note: • Data transfer • controller (DTC) • • • • External Bus bus controller • extension (BSC) • • Notes: 1. DRAM ...
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H8S/2426, H8S/2426R, H8S/2424 Group Module/ Type Function Description • Clock Clock pulse generator • (CPG) • • A/D A/D converter converter • (ADC) • • • • • • D/A D/A converter converter • (DAC) • REJ09B0466-0350 Rev. 3.50 Jul ...
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Section 1 Overview Module/ Type Function Description • Timer 16-bit timer pulse unit • (TPU) • • • • • • • 8-bit timer (TMR) • • • Programma ble pulse • generator (PPG) • • Watchdog Watchdog timer timer ...
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H8S/2426, H8S/2426R, H8S/2424 Group Module/ Type Function Description 2 • High bus function interface 2 • communi- (IIC2) • cations • • • • Synchronou s serial • communicati • on unit • (SSU) • I/O ports H8S/2426 ...
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Section 1 Overview Module/ Type Function Description • Operating frequency/ power supply voltage • • −20°C to +75°C (regular specifications) Operating environment temperature (°C) −40°C to +85°C (wide-range specifications) Page 8 of 1372 Operating frequency MHz Power ...
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H8S/2426, H8S/2426R, H8S/2424 Group 1.2 List of Products Table 1.2 lists the products and figure 1.1 shows how to read the product type name. Table 1.2 Product Code Lineup Product Type Type Code H8S/2426R R4F24269NVRFQV 256 Kbytes Group R4F24268NVRFQV 256 ...
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... Section 1 Overview Product Type Type Code H8S/2426 Group R4F24269NVFQV R4F24268NVFQV R4F24265NVFQV R4S24262NVFQV R4S24261NVFQV R4F24269NFQV R4F24268NFQV R4F24265NFQV R4S24262NFQV R4S24261NFQV R4F24269DVFQV R4F24268DVFQV R4F24265DVFQV R4S24262DVFQV R4S24261DVFQV R4F24269DFQV R4F24268DFQV R4F24265DFQV R4S24262DFQV R4S24261DFQV R4F24269NVLPV R4F24268NVLPV R4F24265NVLPV R4S24262NVLPV R4S24261NVLPV R4F24269NLPV R4F24268NLPV R4F24265NLPV R4S24262NLPV R4S24261NLPV Page 10 of 1372 ...
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H8S/2426, H8S/2426R, H8S/2424 Group Product Type Type Code H8S/2426 Group R4F24269DVLPV R4F24268DVLPV R4F24265DVLPV R4S24262DVLPV R4S24261DVLPV R4F24269DLPV R4F24268DLPV R4F24265DLPV R4S24262DLPV R4S24261DLPV H8S/2424 Group R4F24249NVFAU R4F24248NVFAU R4F24245NVFAU R4S24242NVFAU R4S24241NVFAU R4F24249NFAU R4F24248NFAU R4F24245NFAU R4S24242NFAU R4S24241NFAU R4F24249DVFAU R4F24248DVFAU R4F24245DVFAU R4S24242DVFAU R4S24241DVFAU R4F24249DFAU R4F24248DFAU R4F24245DFAU ...
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Section 1 Overview Product Type Type Code H8S/2424 Group R4F24249NVFPV R4F24248NVFPV R4F24245NVFPV R4S24242NVFPV R4S24241NVFPV R4F24249NFPV R4F24248NFPV R4F24245NFPV R4S24242NFPV R4S24241NFPV R4F24249DVFPV R4F24248DVFPV R4F24245DVFPV R4S24242DVFPV R4S24241DVFPV R4F24249DFPV R4F24248DFPV R4F24245DFPV R4S24242DFPV R4S24241DFPV Page 12 of 1372 Flash Operating Memory Size RAM Size Voltage ...
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H8S/2426, H8S/2426R, H8S/2424 Group Product type name 2426 Figure 1.1 Meaning of Product Type Name REJ09B0466-0350 Rev. 3.50 Jul 09, 2010 Section 1 Overview Indicates treatment of outer leads V: Sn-2Bi ...
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Section 1 Overview 1.3 Block Diagrams MD2 MD1 MD0 EXTAL XTAL EMLE STBY RES WDTOVF NMI PF7/φ PF6/AS/AH PF5/RD PF4/HWR PF3/LWR /SSO0 PF2/LCAS /DQML /IRQ15-A /SSI0 PF1/UCAS /DQMU /IRQ14-A /SSCK0-C PF0/WAIT-A /ADTRG0-B/SCS0-C PG6/BREQ-A PG5/BACK-A PG4/BREQO-A PG3/CS3/RAS3 ...
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H8S/2426, H8S/2426R, H8S/2424 Group MD2 MD1 MD0 EXTAL XTAL EMLE STBY RES WDTOVF NMI PF7/φ PF6/AS/AH PF5/RD PF4/HWR PF3/LWR/SSO0-C PF2/CS6/LCAS*/SSI0-C PF1/CS5/UCAS*/SSCK0-C PF0/WAIT-A/OE-A* /SCS0-C /ADTRG0-B PG6/BREQ-A PG5/BACK-A PG4/BREQO-A/CS4 PG3/CS3/RAS3* PG2/CS2/RAS2* PG1/CS1 PG0/CS0 P85/PO5-B/TIOCB4-B/TMO1-B/SCK3 P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3 P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3 Note: * Not included in the ...
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Section 1 Overview 1.4 Pin Description 1.4.1 Pin Assignments 4 1 PG2/CS2/RAS2 * /RAS * 4 1 PG3/CS3/RAS3 * /CAS * AVcc Vref P40/AN0_0 P41/AN1_0 P42/AN2_0 P43/AN3_0 P44/AN4_0 P45/AN5_0 P46/AN6_0 P47/AN7_0 P90/AN8_1 P91/AN9_1 P92/AN10_1 P93/AN11_1 P94/AN12_1/DA2 P95/AN13_1/DA3 P96/AN14_1 P97/AN15_1 AVss ...
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H8S/2426, H8S/2426R, H8S/2424 Group Vss MD1 MD0 P32 B MD2 Vcc P31 P34 C PC0 P80 PC1 P30 D PC4 PC2 PC3 P53 E PC7 Vss PC5 PB0 F PB3 PC6 PB1 Vss G PB6 PB2 ...
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Section 1 Overview PG2/CS2/RAS2* PG3/CS3/RAS3* AV P40/IRQ0-B/AN0_0 P41/IRQ1-B/AN1_0 P42/IRQ2-B/AN2_0 P43/IRQ3-B/AN3_0 P44/IRQ4-B/AN4_0 P45/IRQ5-B/AN5_0 P46/IRQ6-B/AN6_0 P47/IRQ7-B/AN7_0 P94/AN12_1/DA2 P95/AN13_1/DA3 AV PG4/BREQO-A/CS4/ETCK * PG5/BACK-A/ETMS * PG6/BREQ-A/ETDI * P50/BREQO-B/IRQ0-A/PO0-B/TIOCA3-B/TMRI0-B/TxD2/SDA3 P51/BREQ-B/IRQ1-A/PO2-B/TIOCC3-B/TMCI0-B/RxD2/SCL3 P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/TMO0-B/SCK2 P53/IRQ3-A/ADTRG0-A/ETRST * 3 P35/OE-B * /SCK1/SCL0 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD MD0 MD1 Notes: ...
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H8S/2426, H8S/2426R, H8S/2424 Group 1.4.2 Pin Assignments in Each Operating Mode Table 1.3 Pin Assignments in Each Operating Mode of H8S/2426 Group and H8S/2426R Group Pin No. PLQP0144KA-A PTLG0145JB-A Mode MD2 2 A1 Vss 3 C2 P80/IRQ0-B/ ...
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Section 1 Overview Pin No. PLQP0144KA-A PTLG0145JB-A Mode A17 25 H1 Vss 26 J2 A18 27 H3 A19 28 K4 A20/IRQ4 PA5/A21/ IRQ5-A/ SSCK0 PA6/A22/ IRQ6-A/SSI0 PA7/A23/ IRQ7-A/ SSO0 ...
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H8S/2426, H8S/2426R, H8S/2424 Group Pin No. PLQP0144KA-A PTLG0145JB-A Mode 1 NMI VCL 42 N3 P10/PO8/ TIOCA0 43 M4 P11/PO9/ TIOCB0 44 L4 P12/PO10/ TIOCC0/ TCLKA 45 M5 P13/PO11/ TIOCD0/ TCLKB 46 N4 P14/PO12/ TIOCA1/ SSO0-A 47 ...
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Section 1 Overview Pin No. PLQP0144KA-A PTLG0145JB-A Mode P23/IRQ11-B/ PO3-A/ TIOCD3-A/ TxD4 P24/IRQ12-B/ PO4-A/ TIOCA4-A/ RxD4 P25/WAIT-B/ IRQ13-B/ PO5-A/ TIOCB4 P26/IRQ14-B/ PO6/TIOCA5/ SDA2/ ADTRG1 58 K7 P27/IRQ15-B/ PO7/TIOCB5/ SCL2 59 K8 ...
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H8S/2426, H8S/2426R, H8S/2424 Group Pin No. PLQP0144KA-A PTLG0145JB-A Mode 1 69 M10 PE6/D6/AD6 70 M11 Vss 71 N11 PE7/D7/AD7 72 N12 Vcc 73 M13 D8/AD8 74 N13 D9/AD9 75 L12 D10/AD10 76 M12 D11/AD11 77 L11 D12/AD12 78 L13 D13/AD13 ...
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Section 1 Overview Pin No. PLQP0144KA-A PTLG0145JB-A Mode 1 91 H13 PLLVcc RES 92 G11 93 G13 PLLVss 94 F10 PF7/φ 95 F11 Vss 96 F12 XTAL 97 F13 EXTAL 98 E11 Vcc 99 E13 Vcc 100 D11 PJ0 101 ...
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H8S/2426, H8S/2426R, H8S/2424 Group Pin No. PLQP0144KA-A PTLG0145JB-A Mode 1 117 A10 P44/AN4_0 118 B9 P45/AN5_0 119 C9 P46/AN6_0 120 B8 P47/AN7_0 121 A9 P90/AN8_1 122 D9 P91/AN9_1 123 C8 P92/AN10_1 124 B7 P93/AN11_1 125 A8 P94/AN12_1/ DA2 126 D8 ...
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Section 1 Overview Pin No. PLQP0144KA-A PTLG0145JB-A Mode 1 135 C6 P52/BACK-B/ IRQ2-A/ PO4-B/ TIOCA4-B/ TMO0-B/SCK2 136 D4 P53/IRQ3-A/ ADTRG0-A 137 A5 P35/OE-B* CKE-B* SCK1/SCL0 138 B4 P34/SCK0/ SCK4-A/SDA0 139 C5 P33/RxD1/ SCL1 140 A4 P32/RxD0/ IrRxD/SDA1 141 B3 P31/TxD1 ...
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H8S/2426, H8S/2426R, H8S/2424 Group Table 1.4 Pin Assignments in Each Operating Mode of H8S/2424 Group Pin No. PLQP0120LA-A, PLQP0120KA-A Mode 1 1 MD2 2 Vcc Vss ...
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Section 1 Overview Pin No. PLQP0120LA-A, PLQP0120KA-A Mode 1 28 PA6/A22/ IRQ6-A/SSI0-B 29 PA7/A23/CS7/ IRQ7-A/SSO0-B 30 EMLE WDTOVF 31 NMI 32 33 VCL 34 P10/DREQ0/ PO8/TIOCA0 35 P11/DREQ1/ PO9/TIOCB0 36 P12/TEND0/ PO10/TIOCC0/ TCLKA 37 P13/TEND1/ PO11/TIOCD0/ TCLKB 38 P14/DACK0/ PO12/TIOCA1/ ...
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H8S/2426, H8S/2426R, H8S/2424 Group Pin No. PLQP0120LA-A, PLQP0120KA-A Mode 1 45 P23/PO3-A/ TIOCD3-A/ TMCI1-A/TxD4-A 46 P24/PO4-A/ TIOCA4-A/ TMO0-A/RxD4-A 47 P25/WAIT-B/ PO5-A/ TIOCB4-A/ TMO1-A 48 P26/PO6/ TIOCA5/SDA2/ ADTRG1 49 P27/PO7/ TIOCB5/SCL2 50 P85/PO5-B/ TIOCB4-B/ TMO1-B/SCK3 51 PE0/D0/AD0 52 PE1/D1/AD1 53 PE2/D2/AD2 ...
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Section 1 Overview Pin No. PLQP0120LA-A, PLQP0120KA-A Mode 1 69 PF0/WAIT-A/ OE-A*/ ADTRG0-B/ SCS0-C 70 PF1/CS5/UCAS*/ SSCK0-C 71 PF2/CS6/ LCAS*/SSI0-C 72 PF3/LWR/ SSO0-C HWR PF6/AS/AH 76 PLLVcc RES 77 78 PLLVss 79 PF7/φ 80 Vss 81 ...
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H8S/2426, H8S/2426R, H8S/2424 Group Pin No. PLQP0120LA-A, PLQP0120KA-A Mode 1 95 P40/IRQ0-B/ AN0_0 96 P41/IRQ1-B/ AN1_0 97 P42/IRQ2-B/ AN2_0 98 P43/IRQ3-B/ AN3_0 99 P44/IRQ4-B/ AN4_0 100 P45/IRQ5-B/ AN5_0 101 P46/IRQ6-B/ AN6_0 102 P47/IRQ7-B/ AN7_0 103 P94/AN12_1/DA2 P94/AN12_1/DA2 P94/AN12_1/DA2 P94/AN12_1/DA2 P94/AN12_1/DA2 ...
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Section 1 Overview Pin No. PLQP0120LA-A, PLQP0120KA-A Mode 1 113 P35/OE-B*/ SCK1/SCL0 114 P34/SCK0/ SCK4-A/SDA0 115 P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 P33/RxD1/SCL1 116 P32/RxD0/ IrRxD/SDA1 117 P31/TxD1 118 P30/TxD0/IrTxD 119 MD0 120 MD1 Note: Not supported in the 5-V version. * Page ...
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H8S/2426, H8S/2426R, H8S/2424 Group 1.4.3 Pin Functions Table 1.5 Pin Functions Pin No. H8S/2426, H8S/2426R Type Symbol PLQP0144KA-A PTLG0145JB-A Power V 4, 72, 98, CC supply 10, 18, SS 25, 50, 70, 95, 102 PLLV 91 CC ...
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Section 1 Overview Pin No. H8S/2426, H8S/2426R Type Symbol PLQP0144KA-A PTLG0145JB-A Operating MD2 1 mode MD1 144 control MD0 143 RES System 92 control STBY 103 EMLE 32 Address A23 26, bus 24 to 19, 17 ...
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H8S/2426, H8S/2426R, H8S/2424 Group Pin No. H8S/2426, H8S/2426R Type Symbol PLQP0144KA-A PTLG0145JB-A CS7 to Bus 38 to 35, CS0 control 110 to 107 HWR 88 LWR 87 BREQ-A 132 BREQ-B 134 BREQO-A 130 BREQO-B ...
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Section 1 Overview Pin No. H8S/2426, H8S/2426R Type Symbol PLQP0144KA-A PTLG0145JB-A 1 Bus DQMU* 85 control 1 DQML* 86 RAS2* 3 109 RAS3* 3 110 RAS4 RAS5 RAS* 1 109 CAS* 1 ...
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H8S/2426, H8S/2426R, H8S/2424 Group Pin No. H8S/2426, H8S/2426R Type Symbol PLQP0144KA-A PTLG0145JB-A NMI Interrupt 40 signals IRQ15-A to 86, 85, IRQ8-A* 2 106 to 104 IRQ7 28, IRQ0-A 136 to 133 IRQ15 ...
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Section 1 Overview Pin No. H8S/2426, H8S/2426R Type Symbol PLQP0144KA-A PTLG0145JB-A 16-bit timer TCLKH 22 pulse TCLKG 20 unit (TPU) TCLKF 17 TCLKE 16 TCLKD 49 TCLKC 47 TCLKB 45 TCLKA 44 TIOCA0 42 TIOCB0 43 TIOCC0 44 TIOCD0 45 ...
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H8S/2426, H8S/2426R, H8S/2424 Group Pin No. H8S/2426, H8S/2426R Type Symbol PLQP0144KA-A PTLG0145JB-A 16-bit timer TIOCA6 14 pulse TIOCB6 15 unit (TPU) TIOCC6 16 TIOCD6 17 TIOCA7 19 TIOCB7 20 TIOCA8 21 TIOCB8 22 TIOCA9 5 TIOCB9 6 TIOCC9 7 TIOCD9 ...
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Section 1 Overview Pin No. H8S/2426, H8S/2426R Type Symbol PLQP0144KA-A PTLG0145JB-A 8-bit timer TMO0-A 105 (TMR) TMO1-A 106 TMO0-B 135 TMO1-B 61 TMCI0-A 83 TMCI1-A 104 TMCI0-B 134 TMCI1-B 59 TMRI0-A 81 TMRI1-A 82 TMRI0-B 133 TMRI1-B 33 WDTOVF Watchdog ...
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H8S/2426, H8S/2426R, H8S/2424 Group Pin No. H8S/2426, H8S/2426R Type Symbol PLQP0144KA-A PTLG0145JB-A Serial SCK4-A 138 commu- SCK4-B 27 nication SCK3 61 interface (SCI)/ SCK2 135 Smart Card SCK1 137 interface (SCI_0 SCK0 138 with IrDA function bus ...
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Section 1 Overview Pin No. H8S/2426, H8S/2426R Type Symbol PLQP0144KA-A PTLG0145JB-A 2 A/D AN15_1* 128 converter 2 AN14_1* 127 AN13_1 126 AN12_1 125 AN11_1 to 124 to 121 2 AN8_1* AN7_0 to 120 to 113 AN0_0 ADTRG0-A 136 ADTRG0-B 84 ...
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H8S/2426, H8S/2426R, H8S/2424 Group Pin No. H8S/2426, H8S/2426R Type Symbol PLQP0144KA-A PTLG0145JB-A I/O ports P47 to 120 to 113 P40 P53 to 136 to 133 P50 P65 to 106 to 104, 2 P60 P85 61 2 P84* ...
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Section 1 Overview Pin No. H8S/2426, H8S/2426R Type Symbol PLQP0144KA-A PTLG0145JB-A I/O ports PF7 to 94, PF0 PG6 to 132 to 130, PG0 110 to 107 PH3 PH0* 2 PJ2 ...
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H8S/2426, H8S/2426R, H8S/2424 Group The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear ...
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Section 2 CPU 16 ÷ 8-bit register-register divide: 12 states 16 × 16-bit register-register multiply: 3 states 32 ÷ 16-bit register-register divide: 20 states • Two CPU operating modes Normal mode* Advanced mode Note: * Normal mode is not available ...
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H8S/2426, H8S/2426R, H8S/2424 Group Instruction Mnemonic MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd CLRMAC CLRMAC LDMAC LDMAC ERs, MACH LDMAC ERs, MACL STMAC STMAC MACH, ERd STMAC MACL, ERd Note: * The number ...
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Section 2 CPU • Higher speed Basic instructions execute twice as fast. Note: Normal mode is not available in this LSI. 2.1.3 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements. • ...
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H8S/2426, H8S/2426R, H8S/2424 Group 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-Kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by ...
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Section 2 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Figure 2.1 Exception Vector Table (Normal Mode) SP (16 bits) (a) Subroutine Branch Notes: 1. When EXR is not used not stored on ...
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H8S/2426, H8S/2426R, H8S/2424 Group 2.2.2 Advanced Mode • Address Space Linear access is provided to a 16-Mbyte maximum address space. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers the upper ...
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Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the ...
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H8S/2426, H8S/2426R, H8S/2424 Group 2.3 Address Space Figure 2.5 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-Kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space ...
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Section 2 CPU 2.4 Registers The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC bit extended register ...
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H8S/2426, H8S/2426R, H8S/2424 Group 2.4.1 General Registers The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as ...
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Section 2 CPU SP (ER7) 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit ...
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H8S/2426, H8S/2426R, H8S/2424 Group 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on ...
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Section 2 CPU Bit Bit Name Initial Value 2 Z Undefined 1 V Undefined 0 C Undefined 2.4.5 Multiply-Accumulate Register (MAC) This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32- bit registers denoted MACH and ...
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H8S/2426, H8S/2426R, H8S/2424 Group 2.5 Data Formats The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit …, 7) ...
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Section 2 CPU Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register ...
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H8S/2426, H8S/2426R, H8S/2424 Group 2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If ...
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Section 2 CPU 2.6 Instruction Set The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV 1 POP* , PUSH* LDM, STM MOVFPE* Arithmetic ...
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H8S/2426, H8S/2426R, H8S/2424 Group 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in this LSI. 4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 2.6.1 Table of ...
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Section 2 CPU Symbol Description → Move ∼ NOT (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers ( E7), and ...
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H8S/2426, H8S/2426R, H8S/2424 Group Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD B/W/L Performs addition or subtraction on data in two general registers SUB immediate data ...
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Section 2 CPU Table 2.4 Arithmetic Operations Instructions (2) 1 Instruction Size* Function Rd ÷ Rs → Rd DIVXS B/W Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit ...
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H8S/2426, H8S/2426R, H8S/2424 Group Table 2.5 Logic Operations Instructions Instruction Size* Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd AND B/W/L Performs a logical AND operation on a general register and another general register or immediate data. ...
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Section 2 CPU Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate ...
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H8S/2426, H8S/2426R, H8S/2424 Group Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function C ⊕ (<bit-No.> of <EAd>) → C BXOR B Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the ...
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Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function ⎯ Bcc Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) ...
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H8S/2426, H8S/2426R, H8S/2424 Group Table 2.9 System Control Instructions Instruction Size* Function ⎯ TRAPA Starts trap-instruction exception handling. ⎯ RTE Returns from an exception-handling routine. ⎯ SLEEP Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR ...
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Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function ⎯ if R4L ≠ 0 then EEPMOV.B else next; ⎯ ≠ 0 then EEPMOV.W else next; Transfers a data block. Starting from the address set in ...
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H8S/2426, H8S/2426R, H8S/2424 Group (1) Operation field only (2) Operation field and register fields op (3) Operation field, register fields, and effective address extension op (4) Operation field, effective address extension, and condition field op Figure 2.11 Instruction Formats (Examples) ...
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Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. The usable address modes are different in each instruction. Arithmetic and logic instructions can use the register direct ...
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H8S/2426, H8S/2426R, H8S/2424 Group 2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction code, and the ...
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Section 2 CPU Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction 24 bits (@aa:24) address Note: * Not available in this LSI. 2.7.6 Immediate—#xx:8/#xx:16/#xx:32 The instruction code ...
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H8S/2426, H8S/2426R, H8S/2424 Group 2.7.8 Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits ...
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Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: ...
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H8S/2426, H8S/2426R, H8S/2424 Group Table 2.13 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate Note: * Normal mode is not available in this LSI. REJ09B0466-0350 Rev. 3.50 Jul 09, 2010 Effective Address Calculation PC contents Sign ...
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Section 2 CPU 2.8 Processing States The H8S/2600 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset State The CPU ...
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H8S/2426, H8S/2426R, H8S/2424 Group Bus-released state Exception handling state RES = High Reset state * 1 Reset state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever the RES pin goes low. ...
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Section 2 CPU 2.9 Usage Note 2.9.1 Usage Notes on Bit-wise Operation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in byte-wise, operate the data in bit-wise, and write the result of the bit-wise ...
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H8S/2426, H8S/2426R, H8S/2424 Group Section 3 MCU Operating Modes 3.1 Operating Mode Selection The H8S/2426 Group, H8S/2426R Group, and H8S/2424 Group have five operating modes (modes and 7). The operating mode is selected by the setting of ...
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Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to operating mode setting. • Mode control register (MDCR) • System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR monitors the current operating mode of this ...
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H8S/2426, H8S/2426R, H8S/2424 Group Bit Bit Name Initial Value ⎯ FLSHE 0 ⎯ ⎯ 1 EXPE 0 RAME 1 REJ09B0466-0350 Rev. 3.50 Jul 09, 2010 R/W Descriptions R/W Reserved The initial value should not be ...
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Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports function as an address bus, ports D and ...
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H8S/2426, H8S/2426R, H8S/2424 Group 3.3.4 Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. The program in the on-chip ROM connected to the first half of area 0 is executed. Ports ...
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Section 3 MCU Operating Modes 3.3.6 Pin Functions Table 3.2 shows the pin functions in each operating mode. Table 3.2 Pin Functions in Each Operating Mode Port Port A PA7 to PA5 PA4 to PA0 Port B Port C Port ...
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H8S/2426, H8S/2426R, H8S/2424 Group RAM: 64 Kbytes/48 Kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 External address space H'FE8000 Reserved area * H'FEC000 On-chip RAM/External address space/ Reserved area * H'FF0000 O n-chip RAM/External address space* ...
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Section 3 MCU Operating Modes ROM: 256 Kbytes RAM: 64 Kbytes / 48 Kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'040000 Reserved area*4 H'080000 External address space H'F00000 Data flash area 8 Kbytes H'F02000 External ...
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H8S/2426, H8S/2426R, H8S/2424 Group RAM: 48 Kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 External address H'FE8000 Reserved area * H'FF0000 On-chip RAM/ External address space * H'FFC000 Reserved area * H'FFD000 External address space H'FFFA00 ...
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Section 3 MCU Operating Modes ROM: 128 Kbytes RAM: 48 Kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'020000 Reserved area* H'080000 External address space H'F00000 Data flash area 8 Kbytes H'F02000 External address space H'FE8000 ...
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H8S/2426, H8S/2426R, H8S/2424 Group H'000000 H'FE8000 H'FEC000 H'FF0000 H'FFC000 H'FFD000 H'FFFA00 H'FFFF00 H'FFFF20 H'FFFFFF Notes: 1. This area is specified as the external address space by clearing the RAME bit in SYSCR reserved area should not ...
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Section 3 MCU Operating Modes Page 94 of 1372 H8S/2426, H8S/2426R, H8S/2424 Group REJ09B0466-0350 Rev. 3.50 Jul 09, 2010 ...
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H8S/2426, H8S/2426R, H8S/2424 Group Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, illegal instruction, or trap instruction. Exception handling is prioritized as shown in ...
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Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Since the usable modes differ depending on the product, for ...
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H8S/2426, H8S/2426R, H8S/2424 Group Exception Source External interrupt IRQ7 5 IRQ8* 5 IRQ9* IRQ10* IRQ11* IRQ12* External interrupt IRQ13* IRQ14* IRQ15* 4 Internal interrupt* Notes: 1. Lower 16 bits of the address. 2. Not available in this LSI. 3. Not ...
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Section 4 Exception Handling 4.3 Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low ...
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H8S/2426, H8S/2426R, H8S/2424 Group φ RES Internal address bus Internal read signal Internal write signal Internal data bus (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start ...
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Section 4 Exception Handling φ RES Address bus RD HWR, LWR D15 to D0 (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First ...
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H8S/2426, H8S/2426R, H8S/2424 Group 4.4 Trace Exception Handling Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details on interrupt control modes, ...
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Section 4 Exception Handling 4.5 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. The ...
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H8S/2426, H8S/2426R, H8S/2424 Group 4.6 Trap Instruction Exception Handling Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling ...
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Section 4 Exception Handling 4.7 Illegal Instruction Exception Handling Illegal instruction exception handling starts when the CPU executing an illegal instruction code is detected. Illegal instruction exception handling can be executed at all times in the program execution state. The ...
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H8S/2426, H8S/2426R, H8S/2424 Group 4.8 Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Normal Modes * 2 Advanced Modes Notes: 1. Ignored on return. 2. Normal modes ...
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Section 4 Exception Handling 4.9 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the ...
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). • Priorities ...
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Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 INTCR NMIEG NMI input NMI input unit IRQ input unit IRQ input ISR ITSR ISCR Internal interrupt sources SWDTEND to SSTXI Interrupt ...
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H8S/2426, H8S/2426R, H8S/2424 Group 5.2 Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name I/O NMI Input IRQ15-A to IRQ0-A* Input IRQ15-B to IRQ0-B* IRQ7-A to IRQ0-A and IRQ7-B to IRQ0-B in ...
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Section 5 Interrupt Controller 5.3 Register Descriptions The interrupt controller has the following registers. • Interrupt control register (INTCR) • IRQ sense control register H (ISCRH) • IRQ sense control register L (ISCRL) • IRQ enable register (IER) • IRQ ...
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H8S/2426, H8S/2426R, H8S/2424 Group 5.3.1 Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Bit Name Initial Value ⎯ All 0 5 INTM1 0 4 INTM0 0 3 NMIEG 0 ...
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Section 5 Interrupt Controller 5.3.2 Interrupt Priority Registers (IPRA to IPRN) IPR are eleven 16-bit readable/writable registers that set priorities (levels for interrupts other than NMI. The correspondence between interrupt sources and IPR settings ...
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H8S/2426, H8S/2426R, H8S/2424 Group Bit Bit Name Initial Value ⎯ IPR6 1 5 IPR5 1 4 IPR4 1 ⎯ IPR2 1 1 IPR1 1 0 IPR0 1 REJ09B0466-0350 Rev. 3.50 Jul 09, 2010 R/W ...
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Section 5 Interrupt Controller 5.3.3 IRQ Enable Register (IER) IER controls enabling and disabling of interrupt requests IRQ15 to IRQ0. Bit Bit Name Initial Value 15 IRQ15E 0 14 IRQ14E 0 13 IRQ13E 0 12 IRQ12E 0 11 IRQ11E 0 ...
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H8S/2426, H8S/2426R, H8S/2424 Group Bit Bit Name Initial Value 5 IRQ5E 0 4 IRQ4E 0 3 IRQ3E 0 2 IRQ2E 0 1 IRQ1E 0 0 IRQ0E 0 Note: These bits are reserved in the H8S/2424 Group. * REJ09B0466-0350 Rev. 3.50 ...
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Section 5 Interrupt Controller 5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCR select the source that generates an interrupt request at pins IRQ15 to IRQ0. • ISCRH (H8S/2426 Group only) Bit Bit Name Initial Value 15 IRQ15SCB ...
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H8S/2426, H8S/2426R, H8S/2424 Group Bit Bit Name Initial Value 9 IRQ12SCB 0 8 IRQ12SCA 0 7 IRQ11SCB 0 6 IRQ11SCA 0 5 IRQ10SCB 0 4 IRQ10SCA 0 REJ09B0466-0350 Rev. 3.50 Jul 09, 2010 R/W Description R/W IRQ12 Sense Control B ...
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Section 5 Interrupt Controller Bit Bit Name Initial Value 3 IRQ9SCB 0 2 IRQ9SCA 0 1 IRQ8SCB 0 0 IRQ8SCA 0 Page 118 of 1372 H8S/2426, H8S/2426R, H8S/2424 Group R/W Description R/W IRQ9 Sense Control B R/W IRQ9 Sense Control ...
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H8S/2426, H8S/2426R, H8S/2424 Group • ISCRL Bit Bit Name Initial Value 15 IRQ7SCB 0 14 IRQ7SCA 0 13 IRQ6SCB 0 12 IRQ6SCA 0 11 IRQ5SCB 0 10 IRQ5SCA 0 REJ09B0466-0350 Rev. 3.50 Jul 09, 2010 R/W Description R/W IRQ7 Sense ...
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Section 5 Interrupt Controller Bit Bit Name Initial Value 9 IRQ4SCB 0 8 IRQ4SCA 0 7 IRQ3SCB 0 6 IRQ3SCA 0 5 IRQ2SCB 0 4 IRQ2SCA 0 Page 120 of 1372 H8S/2426, H8S/2426R, H8S/2424 Group R/W Description R/W IRQ4 Sense ...
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H8S/2426, H8S/2426R, H8S/2424 Group Bit Bit Name Initial Value 3 IRQ1SCB 0 2 IRQ1SCA 0 1 IRQ0SCB 0 0 IRQ0SCA 0 REJ09B0466-0350 Rev. 3.50 Jul 09, 2010 R/W Description R/W IRQ1 Sense Control B R/W IRQ1 Sense Control A 00: ...
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Section 5 Interrupt Controller 5.3.5 IRQ Status Register (ISR) ISR is an IRQ15 to IRQ0 interrupt request flag register. Bit Bit Name Initial Value 2 15 IRQ15F IRQ14F IRQ13F IRQ12F* 0 ...
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H8S/2426, H8S/2426R, H8S/2424 Group 5.3.6 IRQ Pin Select Register (ITSR) ITSR selects input pins IRQ15 to IRQ0. • H8S/2426 Group Bit Bit Name Initial Value 15 ITS15 0 14 ITS14 0 13 ITS13 0 12 ITS12 0 11 ITS11 0 ...
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Section 5 Interrupt Controller Bit Bit Name Initial Value 6 ITS6 0 5 ITS5 0 4 ITS4 0 3 ITS3 0 2 ITS2 0 1 ITS1 0 0 ITS0 0 Page 124 of 1372 H8S/2426, H8S/2426R, H8S/2424 Group R/W Description ...
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H8S/2426, H8S/2426R, H8S/2424 Group • H8S/2424 Group Bit Bit Name Initial Value R ⎯ All 0 7 ITS7 0 6 ITS6 0 5 ITS5 0 4 ITS4 0 3 ITS3 0 2 ITS2 0 1 ITS1 0 ...
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Section 5 Interrupt Controller 5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects the IRQ pins used to recover from the software standby state. Bit Bit Name Initial Value 15 SSI15 SSI14 SSI13 ...
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H8S/2426, H8S/2426R, H8S/2424 Group 5.4 Interrupt Sources 5.4.1 External Interrupts The H8S/2426 Group and H8S/2426R Group each have seventeen external interrupts: NMI and IRQ15 to IRQ0. The H8S/2424 Group has nine external interrupts: NMI and IRQ7 to IRQ0. These interrupts ...
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Section 5 Interrupt Controller A block diagram of IRQn interrupts is shown in figure 5.2. IRQnSCA, IRQnSCB Edge/ level detection circuit IRQn input Note for H8S/2426 Group and H8S/2426R Group ...
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H8S/2426, H8S/2426R, H8S/2424 Group 5.5 Interrupt Exception Handling Vector Table Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. When interrupt control mode 2 is ...
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Section 5 Interrupt Controller Origin of Interrupt Interrupt Vector Source Source Number ⎯ Reserved for 36 system use 37 A/D_0 ADI0 38 Reserved for 39 system use TPU_0 TGI0A 40 TGI0B 41 TGI0C 42 TGI0D 43 TCI0V 44 Reserved for ...
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H8S/2426, H8S/2426R, H8S/2424 Group Origin of Interrupt Interrupt Vector Source Source Number TPU_4 TGI4A 64 TGI4B 65 TCI4V 66 TCI4U 67 TPU_5 TGI5A 68 TGI5B 69 TCI5V 70 TCI5U 71 TMR_0 CMIA0 72 CMIB0 73 OVI0 74 Reserved for 75 ...
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Section 5 Interrupt Controller Origin of Interrupt Interrupt Vector Source Source Number SCI_0 ERI0 88 RXI0 89 TXI0 90 TEI0 91 SCI_1 ERI1 92 RXI1 93 TXI1 94 TEI1 95 SCI_2 ERI2 96 RXI2 97 TXI2 98 TEI2 99 SCI_3 ...
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H8S/2426, H8S/2426R, H8S/2424 Group Origin of Interrupt Interrupt Vector Source Source Number IIC2_0 IICI0 116 Reserved for 117 system use IIC2_1 IICI1 118 Reserved for 119 system use TPU_6 TGI6A 120 TGI6B 121 TGI6C 122 TGI6D 123 TCI6V 124 TPU_7 ...
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Section 5 Interrupt Controller Origin of Interrupt Interrupt Vector Source Source Number TPU_11 TGI11A 142 TGI11B 143 TCI11V 144 TCI11U 145 ⎯ Reserved for 146 system use 147 148 149 150 151 152 IIC2_2 IICI2 153 IIC2_3 IICI3 154 SSU ...
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H8S/2426, H8S/2426R, H8S/2424 Group Origin of Interrupt Interrupt Vector Source Source Number ⎯ Reserved for 170 system use | 255 Notes: 1. Lower 16 bits of the start address. 2. Not supported in the H8S/2424 Group. REJ09B0466-0350 Rev. 3.50 Jul ...
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Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is ...
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H8S/2426, H8S/2426R, H8S/2424 Group 5.6.1 Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests except for NMI are masked by the I bit of CCR in the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation ...
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Section 5 Interrupt Controller IRQ0 Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance Page 138 of 1372 Program execution status Interrupt generated? Yes Yes NMI Yes No Yes IRQ1 Yes Save PC and CCR I ...
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H8S/2426, H8S/2426R, H8S/2424 Group 5.6.2 Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level ( bits) in the ...
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Section 5 Interrupt Controller Level 7 interrupt? Yes Mask level 6 or below? Yes Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance Page 140 of 1372 Program execution status No Interrupt generated? Yes Yes NMI Level ...
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H8S/2426, H8S/2426R, H8S/2424 Group 5.6.3 Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack ...
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Section 5 Interrupt Controller Figure 5.5 Interrupt Exception Handling Page 142 of 1372 H8S/2426, H8S/2426R, H8S/2424 Group REJ09B0466-0350 Rev. 3.50 Jul 09, 2010 ...
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H8S/2426, H8S/2426R, H8S/2424 Group 5.6.4 Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in ...
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Section 5 Interrupt Controller Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses Symbol Instruction fetch S I Branch address read S J Stack manipulation S K [Legend] m: Number of wait states in an external device access. ...
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H8S/2426, H8S/2426R, H8S/2424 Group 5.7 Usage Notes 5.7.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared mask interrupts, the masking becomes effective after execution of the instruction. When an interrupt enable bit ...
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Section 5 Interrupt Controller 5.7.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When ...
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H8S/2426, H8S/2426R, H8S/2424 Group 5.7.6 IRQ Status Register (ISR) Depending on the pin status following a reset, IRQnF may be set to 1. Therefore, always read ISR and clear after resets. REJ09B0466-0350 Rev. 3.50 Jul 09, 2010 ...
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Section 5 Interrupt Controller Page 148 of 1372 H8S/2426, H8S/2426R, H8S/2424 Group REJ09B0466-0350 Rev. 3.50 Jul 09, 2010 ...
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation ...
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Section 6 Bus Controller (BSC) • Idle cycle insertion Idle cycles can be inserted between external read cycles to different areas Idle cycles can be inserted before the write cycle after a read cycle Idle cycles can be inserted before ...
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H8S/2426, H8S/2426R, H8S/2424 Group 1 EXDMAC address bus* Internal address bus Internal bus master bus request signal EXDMAC bus request signal* Internal bus master bus acknowledge signal EXDMAC bus acknowledge signal* Internal bus control signals CPU bus request signal DTC ...
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Section 6 Bus Controller (BSC) 6.2 Input/Output Pins Table 6.1 shows the pin configuration of the bus controller. Table 6.1 Pin Configuration Name Address strobe Address hold Read 1 High write/write enable* Low write Chip select 0 Chip select 1 ...
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H8S/2426, H8S/2426R, H8S/2424 Group Name Chip select 4/ 1 row address strobe write enable* Chip select 5/ 1 row address strobe SDRAMφ* Chip select 6 Chip select 7 Upper column address 1 strobe* / ...
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Section 6 Bus Controller (BSC) Name Data transfer acknowledge 1 (DMAC) Data transfer acknowledge 0 (DMAC) Data transfer acknowledge 3* (EXDMAC) 2 Data transfer acknowledge 2* (EXDMAC) Notes: 1. Not supported by the 5-V version. 2. Not supported by the ...
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H8S/2426, H8S/2426R, H8S/2424 Group 6.3 Register Descriptions The bus controller has the following registers. • Bus width control register (ABWCR) • Access state control register (ASTCR) • Wait control register AH (WTCRAH) • Wait control register AL (WTCRAL) • Wait ...
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Section 6 Bus Controller (BSC) 6.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area in the external address space as either 8-bit access space or 16-bit access space. Bit Bit Name Initial Value* 7 ABW7 1/0 6 ABW6 1/0 ...
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H8S/2426, H8S/2426R, H8S/2424 Group 6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL) WTCRA and WTCRB select the number of program wait states for each area in the external address space. In addition, CAS latency ...
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Section 6 Bus Controller (BSC) Bit Bit Name Initial Value 10 W62 1 9 W61 1 8 W60 1 Page 158 of 1372 H8S/2426, H8S/2426R, H8S/2424 Group R/W Description R/W Area 6 Wait Control R/W These bits ...
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H8S/2426, H8S/2426R, H8S/2424 Group • WTCRAL Bit Bit Name Initial Value ⎯ W52 1 5 W51 1 4 W50 1 ⎯ W42 1 1 W41 1 0 W40 1 REJ09B0466-0350 Rev. 3.50 Jul 09, ...
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Section 6 Bus Controller (BSC) • WTCRBH Bit Bit Name Initial Value ⎯ W32 1 13 W31 1 12 W30 1 ⎯ Page 160 of 1372 H8S/2426, H8S/2426R, H8S/2424 Group R/W Description R Reserved This ...
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H8S/2426, H8S/2426R, H8S/2424 Group Bit Bit Name Initial Value 10 W22 1 9 W21 1 8 W20 1 [Legend] X: Don't care. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and * H8S/2424 Group. REJ09B0466-0350 Rev. ...
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Section 6 Bus Controller (BSC) • WTCRBL Bit Bit Name Initial Value ⎯ W12 1 5 W11 1 4 W10 1 ⎯ W02 1 1 W01 1 0 W00 1 Page 162 of 1372 ...
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H8S/2426, H8S/2426R, H8S/2424 Group 6.3.4 Read Strobe Timing Control Register (RDNCR) RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access. Bit Bit Name Initial Value 7 RDN7 0 6 RDN6 0 5 RDN5 ...
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Section 6 Bus Controller (BSC) φ RD RDNn = 0 Data RD RDNn = 1 Data Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space) Page 164 of 1372 Bus cycle H8S/2426, H8S/2426R, H8S/2424 ...
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H8S/2426, H8S/2426R, H8S/2424 Group CS Assertion Period Control Registers H, L (CSACRH, CSACRL) 6.3.5 CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip select signals (CSn) and address signals extended. ...
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Section 6 Bus Controller (BSC) φ Address CS RD Read Data HWR, LWR Write Data Figure 6.3 CS and Address Assertion Period Extension (Example of 3-State Access Space and RDNn = 0) Page 166 of 1372 Bus cycle T T ...
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H8S/2426, H8S/2426R, H8S/2424 Group 6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL) BROMCRH and BROMCRL are used to make burst ROM interface settings. Area 0 and area 1 burst ROM interface ...
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Section 6 Bus Controller (BSC) 6.3.7 Bus Control Register (BCR) BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT ...
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H8S/2426, H8S/2426R, H8S/2424 Group Bit Bit Name Initial Value 10 ICIS0 1 9 WDBE 0 8 WAITE ⎯ All 0 2 ICIS2 0 ⎯ All 0 Note: * The refresh control is not supported ...
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Section 6 Bus Controller (BSC) 6.3.8 Address/Data Multiplexed I/O Control Register (MPXCR) MPXCR is used to make address/data multiplexed I/O interface settings. Bit Bit Name Initial Value 7 MPXE ⎯ All 0 0 ADDEX 0 Page ...