M30626SPGP#U3C Renesas Electronics America, M30626SPGP#U3C Datasheet - Page 104

IC M16C/62P MCU ROMLESS 100LQFP

M30626SPGP#U3C

Manufacturer Part Number
M30626SPGP#U3C
Description
IC M16C/62P MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheet

Specifications of M30626SPGP#U3C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30626SPGP#U3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30626SPGP#U3CM30626SPGP#U5C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 10.5
Processor Mode Register 2
Peripheral Clock Select Register
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
0 0 0 0
1.
2.
3.
4.
5.
1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (w rite enable).
Write to this register after setting the PRC1 bit in the PRCR register to “1” (w rite enable).
The PM20 bit become effective w hen PLC07 bit in the PLC0 register is set to “1” (PLL on). Change the PM20 bit
w hen the PLC07 bit is set to “0” (PLL off). Set the PM20 bit to “0” (2 w aits) w hen PLL clock > 16MHz.
Once this bit is set to “1”, it cannot be cleared to “0” in a program.
If the PM21 bit is set to “1”, w riting to the follow ing bits has no effect:
Be aw are that the WAIT instruction cannot be executed w hen the PM21 bit = 1.
Setting the PM22 bit to “1” results in the follow ing conditions:
• The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the w atchdog timer count source.
• The CM10 bit is disabled against w rite. (Writing a “1” has no effect, nor is stop mode entered.)
• The w atchdog timer does not stop w hen in w ait mode or hold state.
CM02 bit in CM0 register
CM05 bit in CM0 register (main clock does not stop)
CM07 bit in CM0 register (clock source for the CPU clock does not change)
CM10 bit in CM1 register (stop mode is not entered)
CM11 bit in CM1 register (clock source for the CPU clock does not change)
CM20 bit in CM2 register (oscillation stop, re-oscillation detection function settings do not change)
All bits in PLC0 register (PLL frequency synthesizer settings do not change)
0 0
Jan 10, 2006
0 0
PCLKR Register and PM2 Register
Bit Symbol
Bit Symbol
(b4-b3)
(b7-b5)
Symbol
(b7-b2)
Symbol
PCLKR
PCLK0
PCLK1
PM20
PM21
PM22
PM2
Page 87 of 390
(1)
Specifying Wait w hen Accessing
SFR at PLL Operation
System Clock Protective Bit
WDT Count Source
Protective Bit
Reserved Bit
Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
Timers A, B Clock Select Bit
(Clock source for Timers A , B, and the dead timer)
SI/O Clock Select Bit
(Clock source for UART0 to UART2, SI/O3, and
SI/O4)
Reserved bit
(1)
Address
Bit Name
(3, 5)
001Eh
(2)
Address
Bit Name
025Eh
(3, 4)
0 : 2 w aits
1 : 1 w aits
0 : Clock is protected by PRCR register
1 : Clock modification disabled
0 : CPU clock is used for the w atchdog timer
1 : On-chip oscillator clock is used for the
Set to “0”
count source
w atchdog timer count source
After Reset
XXX00000b
0 : f2
1 : f1
0 : f2SIO
1 : f1SIO
Set to “0”
Function
10. Clock Generation Circuit
After Reset
00000011b
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW

Related parts for M30626SPGP#U3C