M30626SPGP#U3C Renesas Electronics America, M30626SPGP#U3C Datasheet - Page 142

• Manufacturer Part Number: M30626SPGP#U3C
• Description: IC M16C/62P MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626SPGP#U3C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 13.2
13.1
Watchdog Timer Start Register
Watchdog Timer Control Register
In this mode, a on-chip oscillator clock is used for the watchdog timer count source. The watchdog timer can be
kept being clocked even when CPU clock stops as a result of run-away.
Before this mode can be used, the following register settings are required:
Setting the PM22 bit in the PM register to “1” results in the following conditions.
Watchdog timer period
b7
NOTES :
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
(1) Set the PRC1 bit in the PRCR register to “1” (enable writes to PM1 and PM2 registers).
(2) Set the PM12 bit in the PM1 register to “1” (reset when the watchdog timer underflows).
(3) Set the PM22 bit in the PM2 register to “1” (on-chip oscillator clock used for the watchdog timer count
(4) Set the PRC1 bit in the PRCR register to “0” (disable writes to PM1 and PM2 registers).
(5) Write to the WDTS register (watchdog timer starts counting).
•
•
•
1.
1.
2.
0
The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count
source.
The CM10 bit in the CM1 register is disabled against write (Writing a “1” has no effect, nor is stop mode
entered).
The watchdog timer does not stop when in wait mode or hold state.
Write to the WDTS register after the w atchdog timer interrupt occurs.
Count source protective mode
Writing to the WDC register factors the WDC5 bit to be set to “1” (w arm start). If the voltage applied to VCC1 is less
than 4.0 V, either w rite to this register w hen the CPU clock frequency is 2 MHz or w rite tw ice.
The WDC5 bit is set to “0” (cold start) w hen pow er is turned on and can be set to “1” by program only.
Jan 10, 2006
source).
WDC and WDTS Register
b0
The w atchdog timer is initialized and starts counting after a w rite instruction to this register.
The w atchdog timer value is alw ays initialized to “7FFFh” regardless of w hatever value is
w ritten.
Bit Symbol
Symbol
(b4-b0)
Symbol
WDTS
WDC5
WDC7
WDC
(b6)
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—
—
=
High-order Bit of Watchdog Timer
Cold Start / Warm Start Discrimination
Flag
Reserved Bit
Prescaler Select Bit
(1)
Watchdog timer count (32768)
(1, 2)
On-chip oscillator clock
Address
000Eh
Address
Bit Name
000Fh
Function
0 : Cold Start
1 : Warm Start
Set to “0”
0 : Divided by 16
1 : Divided by 128
Indeterminate
After Reset
00XXXXXXb
After Reset
Function
(2)
13. Watchdog Timer
WO
RW
RW
RW
RW
RW
RO