M30626SPGP#U3C Renesas Electronics America, M30626SPGP#U3C Datasheet - Page 144

• Manufacturer Part Number: M30626SPGP#U3C
• Description: IC M16C/62P MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626SPGP#U3C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Table 14.1
NOTES:
No. of Channels
Transfer Memory Space
Maximum No. of Bytes Transferred
DMA Request Factors
Channel Priority
Transfer Unit
Transfer Address Direction
Transfer Mode
DMA Interrupt Request Generation Timing
DMA Start up
DMA Shutdown
Reload Timing for Forward Address Pointer
and Transfer Counter
DMA Transfer Cycles
1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the interrupt
2. The selectable factors of DMA requests differ with each channel.
3. Make sure that no DMAC-related registers (addresses 0020h to 003Fh) are accessed by the DMAC.
control register.
Jan 10, 2006
DMAC Specifications
Single Transfer
Repeat Transfer
Single Transfer
Repeat Transfer
Item
(1, 2)
Page 127 of 390
2 (cycle steal method)
• From any address in the 1-Mbyte space to a fixed address
• From a fixed address to any address in the 1-Mbyte space
• From a fixed address to a fixed address
Falling edge of INT0 or INT1
Both edge of INT0 or INT1
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transfer, UART0 reception interrupt requests
UART1 transfer, UART1 reception interrupt requests
UART2 transfer, UART2 reception interrupt requests
SI/O3, SI/O4 interrupt requests
A/D conversion interrupt requests
Software triggers
forward or fixed (The source and destination addresses cannot both be
in the forward direction.)
underflows after reaching the terminal count.
of the DMAi transfer counter reload register and a DMA transfer is
continued with it.
When the DMAi transfer counter underflowed
Data transfer is initiated each time a DMA request is generated when the
DMAE bit in the DMAiCON register = 1 (enabled).
• When the DMAE bit is set to “0” (disabled)
• After the DMAi transfer counter underflows
When a data transfer is started after setting the DMAE bit to “1”
(enabled), the forward address pointer is reloaded with the value of the
SARi or the DARi pointer whichever is specified to be in the forward
direction and the DMAi transfer counter is reloaded with the value of the
DMAi transfer counter reload register.
128 Kbytes (with 16-bit transfers) or 64 Kbytes (with 8-bit transfers)
DMA0 > DMA1 (DMA0 takes precedence)
8 bits or 16 bits
Transfer is completed when the DMAi transfer counter (i = 0 to 1)
When the DMAi transfer counter underflows, it is reloaded with the value
When the DMAE bit is set to “0” (disabled)
Minimum 3 cycles between SFR and internal RAM
Specification
14. DMAC