M30626SPGP#U3C Renesas Electronics America, M30626SPGP#U3C Datasheet - Page 222

IC M16C/62P MCU ROMLESS 100LQFP

M30626SPGP#U3C

Manufacturer Part Number
M30626SPGP#U3C
Description
IC M16C/62P MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheet

Specifications of M30626SPGP#U3C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30626SPGP#U3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30626SPGP#U3CM30626SPGP#U5C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
17.1.3
Table 17.10
NOTES:
Transfer Data Format
Transfer Clock
Transmission Start
Condition
Reception Start Condition
Interrupt Request
Generation Timing
Error Detection
Select Function
1. When an external clock is selected, the conditions must be met while the external clock is in the high state.
2. If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit in the SiRIC register does
I
of the I
13.13 lists the I
Transfer to UiRB Register and Interrupt Timing.
As shown in Table 17.13, the microcomputer is placed in I
“010b” and the IICM bit to “1”. Because SDAi transmit output has a delay circuit attached, SDAi output does
not change state until SCLi goes low and remains stably low.
2
not change.
C mode is provided for use as a simplified I
Jan 10, 2006
Special Mode 1 (I
Item
2
C mode. Table 17.11 to 17.12 lists the registers used in the I
I
2
C Mode Specifications
2
C Mode Functions. Figure 17.25 shows the block diagram for I
Page 205 of 390
Transfer data length: 8 bits
• During master
• During slave
Before transmission can start, met the following requirements
• The TE bit in the UiC1 register= 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
Before reception can start, met the following requirements
• The RE bit in UiC1 register= 1 (reception enabled)
• The TE bit in UiC1 register= 1 (transmission enabled)
• The TI bit in UiC1 register= 0 (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
Overrun error
• Arbitration lost
• SDAi digital delay
• Clock phase setting
CKDIR bit in the UiMR (i=0 to 2) register = 0 (internal clock) : fj/ (2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO
CKDIR bit = 1 (external clock) : Input from SCLi pin
This error occurs if the serial interface started receiving the next data before reading
the UiRB register and received the 8th bit of the next data
Timing at which the ABT bit in the UiRB register is updated can be selected
No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable
With or without clock delay selectable
2
C mode)
(2)
2
C interface compatible mode. Table 17.10 lists the specifications
n: Setting value of UiBRG register
Specification
2
C mode by setting the SMD2 to SMD0 bits to
2
C mode and the register values set. Table
2
(1)
C mode. Figure 17.26 shows
(1)
17. Serial Interface
00h to FFh

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