M30626SPGP#U3C Renesas Electronics America, M30626SPGP#U3C Datasheet - Page 239

• Manufacturer Part Number: M30626SPGP#U3C
• Description: IC M16C/62P MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626SPGP#U3C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
17.1.6
Table 17.18
NOTES:
Transfer Data Format
Transfer Clock
Transmission Start
Condition
Reception Start Condition
Interrupt Request
Generation Timing
Error Detection
1. If an overrun error occurs, the value of U2RB register will be indeterminate. The IR bit in the S2RIC register
2. A transmit interrupt request is generated by setting the U2IRS bit to “1” (transmission complete) and U2ERE bit
3. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred
Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be
implemented, and this mode allows to output a low from the TXD2 pin when a parity error is detected.
Table 17.18 lists the SIM Mode Specifications. Table 17.19 lists the Registers to Be Used and Settings in SIM
Mode.
does not change.
to “1” (error signal output) in the U2C1 register after reset is deserted. Therefore, when using SIM mode, set the
IR bit to “0” (no interrupt request) after setting these bits.
from the UARTi receive register to the UiRB register.
Jan 10, 2006
Special Mode 4 (SIM Mode) (UART2)
Item
SIM Mode Specifications
(2)
Page 222 of 390
• Direct format
• Inverse format
• CKDIR bit in U2MR register = 0 (internal clock) : fi/ (16(n+1))
• fi = f1SIO, f2SIO, f8SIO, f32SIO n: Setting value of U2BRG register 00h to FFh
• CKDIR bit = 1 (external clock) : fEXT/(16(n+1))
Before transmission can start, meet the following requirements
• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in U2TB register)
Before reception can start, meet the following requirements
• The RE bit in the U2C1 register = 1 (reception enabled)
• Start bit detection
• For transmission
• For reception
• Overrun error
• Framing error
• Parity error
• Error sum flag
fEXT: Input from CLK2 pin n: Setting value of U2BRG register 00h to FFh
When the serial interface finished sending data from the U2TB transfer register
(U2IRS bit =1)
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
This error occurs if the serial interface started receiving the next data before reading
the U2RB register and received the bit one before the last stop bit of the next data
This error occurs when the number of stop bits set is not detected
During reception, if a parity error is detected, parity error signal is output from the
TXD2 pin.
During transmission, a parity error is detected by the level of input to the RXD2 pin
when a transmission interrupt occurs
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
(3)
(1)
(3)
Specification
17. Serial Interface