M30626SPGP#U3C Renesas Electronics America, M30626SPGP#U3C Datasheet - Page 289

IC M16C/62P MCU ROMLESS 100LQFP

M30626SPGP#U3C

Manufacturer Part Number
M30626SPGP#U3C
Description
IC M16C/62P MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheet

Specifications of M30626SPGP#U3C

Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30626SPGP#U3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Company:
Part Number:
M30626SPGP#U3CM30626SPGP#U5C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
22.1
Figure 22.1
The flash memory contains the user ROM area and the boot ROM area. The user ROM area has space to store the
microcomputer operating program in single-chip mode or memory expansion mode and a separate 4-Kbyte space
as the block A. Figure 22.1 shows a Flash Memory Block Diagram.
The user ROM area is divided into several blocks, each of which can be protected (locked) from program or erase.
The user ROM area can be rewritten in CPU rewrite, standard serial I/O and parallel I/O modes.
Block A is enabled for use by setting the PM10 bit in the PM1 register to “1” (block A enabled, CS2 area at
addresses 10000h to 26FFFh).
The boot ROM area is located at the same addresses as the user ROM area. It can only be rewritten in parallel I/O
mode (refer to 22.1.1 Boot Mode). A program in the boot ROM area is executed after a hardware reset occurs
while an “H” signal is applied to the CNVSS and P5_0 pins and an “L” signal is applied to the P5_5 pin (refer to
22.1.1 Boot Mode). A program in the user ROM area is executed after a hardware reset occurs while an “L” signal
is applied to the CNVSS pin. However, the boot ROM area cannot be read.
00F000h
00FFFFh
080000h
08FFFFh
090000h
09FFFFh
0A0000h
0AFFFFh
0B0000h
0BFFFFh
0C0000h
0CFFFFh
0D0000h
0DFFFFh
0E0000h
0EFFFFh
0F0000h
0FFFFFh
NOTES:
Memory Map
Jan 10, 2006
1. The boot ROM area can only be rewritten in parallel input/output mode.
2. To specify a block, use an even address in that block.
3. Shown here is a block diagram during single-chip mode.
4. Block A can be made usable by setting the PM10 bit in the PM1 register to “1” (block A enabled, CS2 area allocated at addresses 10000h to 26FFFh).
Block A cannot be erased by the Erase All Unlocked Block command. Use the Block Erase command to erase it.
Flash Memory Block Diagram
(32+8+8+8+4+4) Kbytes
Block 12 : 64 Kbytes
Block 11 : 64 Kbytes
Block 10 : 64 Kbytes
Block 9 : 64 Kbytes
Block 8 : 64 Kbytes
Block 7 : 64 Kbytes
Block 6 : 64 Kbytes
Block A : 4 Kbytes
Block 0 to Block 5
Page 272 of 390
User ROM area
0F0000
0F7FFFh
0F8000h
0F9FFFh
0FA000h
0FBFFFh
0FC000h
0FDFFFh
0FE000h
0FEFFFh
0FF000h
0FFFFFh
h
Block 5 : 32 Kbytes
Block 4 : 8 Kbytes
Block 3 : 8 Kbytes
Block 2 : 8 Kbytes
Block 1 : 4 Kbytes
Block 0 : 4 Kbytes
0FF000h
0FFFFFh
22. Flash Memory Version
Boot ROM area
4 Kbytes

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