M30626SPGP#U3C Renesas Electronics America, M30626SPGP#U3C Datasheet - Page 311

• Manufacturer Part Number: M30626SPGP#U3C
• Description: IC M16C/62P MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626SPGP#U3C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 22.14
N O T E : W h e n e ith e r F M R 0 6 o r F M R 0 7 b it is s e t to “1 ” (te rm in a te d b y e rro r ) , th e p ro g ra m , b lo c k e ra s e , e r a s e a ll u n lo c k e d b lo c k ,
F u ll s ta tu s c h e c k c o m p le te d
F u ll s ta tu s c h e c k
lo c k b it p ro g ra m a n d re a d lo c k b it s ta tu s c o m m a n d s c a n n o t b e a c c e p te d .
E x e c u te th e c le a r s ta tu s re g is te r c o m m a n d b e fo re e a c h c o m m a n d .
Jan 10, 2006
F M R 0 7 = 0 ?
F M R 0 6 = 0 ?
F M R 0 7 = 1 ?
F M R 0 6 = 1
a n d
Full Status Check and Handling Procedure for Each Error
Y E S
N O
Y E S
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Y E S
N O
N O
s e q u e n c e e rro r
P ro g ra m e rro r
E ra s e e rro r
C o m m a n d
(1 ) E x e c u te th e c le a r s ta tu s re g is te r c o m m a n d a n d s e t th e S R 4 b it to “0 ”
(2 ) E x e c u te th e re a d lo c k b it s ta tu s c o m m a n d a n d s e t th e F M R 0 2 b it to “1 ”
(3 ) E x e c u te th e p ro g r a m c o m m a n d a g a in .
(1 ) E x e c u te th e c le a r s ta tu s r e g is te r c o m m a n d a n d s e t th e S R 4 b it to “0 ”.
(2 ) S e t th e F M R 0 2 b it in th e F M R 0 re g is te r to “1 ”.
(3 ) E x e c u te th e b lo c k e ra s e c o m m a n d to e ra s e th e b lo c k w h e re th e e rro r
(4 ) E x e c u te th e lo c k b it p ro g r a m c o m m a n d a g a in .
[W h e n a p r o g ra m o p e r a tio n is e x e c u te d ]
[W h e n a lo c k b it p ro g r a m o p e ra tio n is e x e c u te d ]
(1 ) E x e c u te th e c le a r s ta tu s re g is te r c o m m a n d a n d s e t th e S R 5 b it to “0 ”.
(2 ) E x e c u te th e lo c k b it re a d s ta tu s c o m m a n d . S e t th e F M R 0 2 b it to “1 ”
(3 ) E x e c u te th e b lo c k e ra s e o r e ra s e a ll u n lo c k e d b lo c k c o m m a n d a g a in .
(4 ) E x e c u te (1 ), ( 2 ) a n d ( 3 ) a t le a s t 3 tim e s u n til a n e ra s e e rro r is n o t
( 1 ) E x e c u te th e c le a r s ta tu s re g is te r c o m m a n d a n d s e t th e S R 4 a n d S R 5
( 2 ) R e w r ite c o m m a n d a n d e x e c u te a g a in .
( c o m p le te d a s e x p e c te d ) .
if th e lo c k b it in th e b lo c k w h e re th e e r ro r o c c u rr e d is s e t to 0 .
N O T E : W h e n a s im ila r e rro r o c c u r s , th a t b lo c k c a n n o t b e u s e d .
o c c u rre d .
N O T E : If s im ila r e rr o r o c c u rs , th a t b lo c k c a n n o t b e u s e d .
( lo c k b it d is a b le d ) if th e lo c k b it in th e b lo c k w h e re th e e rro r o c c u r re d is
s e t to “0 ” (lo c k e d ).
g e n e ra te d .
N O T E : If s im ila r e rro r o c c u rs , th a t b lo c k c a n n o t b e u s e d .
b its to “0 ” (c o m p le te d a s e x p e c te d ) .
If th e lo c k b it is s e t to “ 1 ” in (2 ) a b o v e , th a t b lo c k c a n n o t b e u s e d .
If th e lo c k b it is s e t to “ 1 ” (u n lo c k e d ) in ( 2 ) a b o v e , th a t b lo c k
c a n n o t b e u s e d .
22. Flash Memory Version