M30626SPGP#U3C Renesas Electronics America, M30626SPGP#U3C Datasheet - Page 76

• Manufacturer Part Number: M30626SPGP#U3C
• Description: IC M16C/62P MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/60r

Specifications of M30626SPGP#U3C

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: I²C, IEBus, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 50
• Program Memory Type: ROMless
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: 867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
8.
During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform data input/
output to and from external devices. These bus control pins include A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/
WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK.
8.1
8.1.1
8.1.2
Table 8.1
NOTES:
P0_0 to P0_7/D0 to D7
P1_0 to P1_7/D8 to D15
P2_0/A0 (/D0/-)
P2_1 to P2_7/A1 to A7
(/D1 to D7/D0 to D6)
P3_0/A8 (/-/D7)
The bus mode, either multiplexed or separate, can be selected using the PM05 to PM04 bits in the PM0 register.
Table 8.1 shows the Difference Between a Separate Bus and Multiplexed Bus.
8.1.2.1
8.1.2.2
Bus
1. See Table 8.6 Pin Functions for Each Processor Mode for bus control signals other than the
2. It changes with a setup of PM05 to PM04, and area to access.
In this bus mode, data and address are separate.
In this bus mode, data and address are multiplexed.
D0 to D7 and A0 to A7 are multiplexed.
D0 to D7 and A1 to A8 are multiplexed. D8 to D15 are not multiplexed. Do not use D8 to D15. External devices
connecting to a multiplexed bus are allocated to only the even addresses of the microcomputer. Odd
addresses cannot be accessed.
Note
The M16C/62P (80-pin version) and M16C/62PT do not use bus control pins.
above. Setting Processor Modes.
See Table 8.6 Pin Functions for Each Processor Mode for details.
Bus Mode
Jan 10, 2006
Pin Name
Separate Bus
Multiplexed Bus
When the input level on BYTE pin is high (8-bit data bus)
When the input level on BYTE pin is low (16-bit data bus)
Difference Between a Separate Bus and Multiplexed Bus
(1)
Page 59 of 390
Separate Bus
D8 to D15
D0 to D7
A1 to A7
A0
A8
A1 to A7
P1_0 to P1_7
A0
BYTE = H
(NOTE 2)
I/O Port
A8
D1 to D7
D0
Multiplex Bus
A1 to A7 D0 to D6
A8
BYTE = L
(NOTE 2)
(NOTE 2)
A0
D7
8. Bus