MC9S12DT256MPVE Freescale Semiconductor, MC9S12DT256MPVE Datasheet
MC9S12DT256MPVE
Specifications of MC9S12DT256MPVE
Available stocks
Related parts for MC9S12DT256MPVE
MC9S12DT256MPVE Summary of contents
Page 1
MC9S12XDP512 Data Sheet Covers S12XD, S12XB & S12XA Families HCS12X Microcontrollers MC9S12XDP512RMV2 Rev. 2.21 October 2009 freescale.com ...
Page 2
...
Page 3
MC9S12XDP512RMV2 Data Sheet MC9S12XDP512RMV2 Rev. 2.21 October 2009 ...
Page 4
... This document contains information for all constituent modules, with the exception of the S12X CPU. For S12X CPU information please refer to the CPU S12X Reference Manual. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. ...
Page 5
... July 2006 June 2007 July 2007 April 2008 August 2008 September 2009 October 2009 Freescale Semiconductor Level 02.07 New Book 02.08 Minor corrections removed ESD Machine Model from electrical characteristics added thermal characteristics added more details to run current measurement configurations 02 ...
Page 6
... MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor ...
Page 7
... S12X Debug (S12XDBGV3) Module . . . . . . . . . . . . . . . . . . . . 745 Chapter 21 External Bus Interface (S12XEBIV2 787 Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2 807 Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2 901 Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2 975 Freescale Semiconductor Title MC9S12XDP512 Data Sheet, Rev. 2.21 Page 5 ...
Page 8
... Security (S12X9SECV2 1231 Appendix A Electrical Characteristics 1239 Appendix B Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1290 Appendix C Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . 1294 Appendix D Using L15Y Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299 Appendix E Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300 Appendix F Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1308 Appendix G Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309 6 Title MC9S12XDP512 Data Sheet, Rev. 2.21 Page Freescale Semiconductor ...
Page 9
... Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 2.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 2.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 2.4.1 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 2.4.2 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 2.4.3 Low Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Freescale Semiconductor Title Chapter 2 — Operating and Ground Voltage Pins . . . . . . . . . . . . . . . . . . . . . 82 MC9S12XDP512 Data Sheet, Rev. 2.21 Page 9 ...
Page 10
... High Reference Voltage Pin, Low Reference Voltage Pin . . . . . . . . . . . . 127 RH RL 4.2 — Analog Circuitry Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . 127 DDA SSA 4.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 10 Title Chapter 3 — Operating and Ground Voltage Pins . . . . . . . . . . . . . . . . . . . . 120 Chapter 4 Block Description MC9S12XDP512 Data Sheet, Rev. 2.21 Page Freescale Semiconductor ...
Page 11
... Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 6.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 6.4.1 XGATE RISC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 6.4.2 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 6.4.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Freescale Semiconductor Title — Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Page ...
Page 12
... IOC0 — Input Capture and Output Compare Channel 311 7.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 7.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 7.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 7.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 7.4.1 Enhanced Capture Timer Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 7.4.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 12 Title Chapter 7 MC9S12XDP512 Data Sheet, Rev. 2.21 Page Freescale Semiconductor ...
Page 13
... Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 9.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 9.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 9.4.1 I-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 9.4.2 Operation in Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 9.4.3 Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 Freescale Semiconductor Title Chapter 8 Chapter 9 MC9S12XDP512 Data Sheet, Rev. 2.21 Page 13 ...
Page 14
... Serial Communication Interface (S12SCIV5) 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 11.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 11.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 11.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 11.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 11.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 14 Title Chapter 10 Chapter 11 MC9S12XDP512 Data Sheet, Rev. 2.21 Page Freescale Semiconductor ...
Page 15
... Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 12.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 12.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 12.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 12.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 12.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 12.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 Freescale Semiconductor Title Chapter 12 MC9S12XDP512 Data Sheet, Rev. 2.21 Page 15 ...
Page 16
... Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 14.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 14.4.2 Regulator Core (REG 564 14.4.3 Low-Voltage Detect (LVD 565 14.4.4 Power-On Reset (POR 565 14.4.5 Low-Voltage Reset (LVR 565 14.4.6 Regulator Control (CTRL 565 16 Title Chapter 13 Chapter 14 MC9S12XDP512 Data Sheet, Rev. 2.21 Page Freescale Semiconductor ...
Page 17
... External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 16.3.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 16.4.1 S12X Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 16.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 Freescale Semiconductor Title Chapter 15 Chapter 16 Interrupt (S12XINTV1) MC9S12XDP512 Data Sheet, Rev. 2.21 ...
Page 18
... S12X Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 18.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 18.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 18.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 18.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656 18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 18 Title Chapter 17 Chapter 18 MC9S12XDP512 Data Sheet, Rev. 2.21 Page Freescale Semiconductor ...
Page 19
... Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 20.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746 20.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 20.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 20.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 20.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 Freescale Semiconductor Title Chapter 19 Chapter 20 MC9S12XDP512 Data Sheet, Rev. 2.21 Page 19 ...
Page 20
... External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 22.2.1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 22.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 22.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817 22.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820 22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881 22.4.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881 20 Title Chapter 21 Chapter 22 MC9S12XDP512 Data Sheet, Rev. 2.21 Page Freescale Semiconductor ...
Page 21
... Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983 24.0.5 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985 Table 24-59.Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028 24.0.6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029 24.0.7 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031 24.0.8 Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033 24.0.9 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1034 24.0.9.3Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035 Freescale Semiconductor Title Chapter 23 Chapter 24 MC9S12XDP512 Data Sheet, Rev. 2.21 Page 21 ...
Page 22
... Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 26.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074 26.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078 26.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086 26.4.1 EEPROM Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086 26.4.2 EEPROM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1089 26.4.3 Illegal EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103 22 Title Chapter 25 Chapter 26 MC9S12XDP512 Data Sheet, Rev. 2.21 Page Freescale Semiconductor ...
Page 23
... Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . 1147 27.7 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147 27.7.1 Flash Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147 27.7.2 Reset While Flash Command Active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147 27.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1147 27.8.1 Description of Flash Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148 Freescale Semiconductor Title Chapter 27 MC9S12XDP512 Data Sheet, Rev. 2.21 Page 23 ...
Page 24
... External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192 29.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193 29.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1193 29.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195 29.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208 29.4.1 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208 29.4.2 Flash Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211 24 Title Chapter 28 Chapter 29 MC9S12XDP512 Data Sheet, Rev. 2.21 Page Freescale Semiconductor ...
Page 25
... A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1244 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1246 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249 A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253 A.2.1 ATD Operating Characteristics 1253 A.2.2 Factors Influencing Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254 A.2.3 ATD Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256 Freescale Semiconductor Title Chapter 30 Security (S12X9SECV2) Appendix A Electrical Characteristics MC9S12XDP512 Data Sheet, Rev. 2.21 ...
Page 26
... E.4 MC9S12XD/A/B -Family SRAM & EEPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 1304 E.5 Peripheral Sets S12XD - Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305 E.6 Peripheral Sets S12XA & S12XB - Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306 26 Title Appendix B Package Information Appendix C Recommended PCB Layout Appendix D Using L15Y Silicon Appendix E Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303 MC9S12XDP512 Data Sheet, Rev. 2.21 Page Freescale Semiconductor ...
Page 27
... Section Number E.7 Pinout explanations 1307 Freescale Semiconductor Title Appendix F Ordering Information Appendix G Detailed Register Map MC9S12XDP512 Data Sheet, Rev. 2.21 Page 27 ...
Page 28
... Section Number 28 Title MC9S12XDP512 Data Sheet, Rev. 2.21 Page Freescale Semiconductor ...
Page 29
... Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2) 1105 Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1) 1147 Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1) 1189 Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV3) 157 Freescale Semiconductor NOTE Table 0-1. Maskset Specific Documentation MC9S12XDP512 Data Sheet, Rev. 2.21 Table 0-1 ...
Page 30
... S12XA, S12XB and S12XD families please refer to Differences. For pinout explanations of the different parts refer to available partnames /masksets refer to 30 describes pinouts, detailed pin description , interrupts Table 1-6. MC9S12XDP512 Data Sheet, Rev. 2.21 Appendix E Derivative E.7 Pinout explanations:. For a list of Freescale Semiconductor ...
Page 31
... Family members in 144-pin LQFP will be available with external bus interface and parts in 112-pin LQFP or 80-pin QFP package without external bus interface. See options. Freescale Semiconductor Appendix E Derivative Differences MC9S12XDP512 Data Sheet, Rev. 2.21 Chapter 1 Device Overview MC9S12XD-Family ...
Page 32
... Memory — 512, 256 and 128-Kbyte Flash EEPROM — 4 and 2-Kbyte EEPROM — 32, 16 and 12-Kbyte RAM • One 16-channel and one 8-channel ADC (analog-to-digital converter) 32 Appendix E Derivative Differences 24 bus clock cycles MC9S12XDP512 Data Sheet, Rev. 2.21 for Freescale Semiconductor ...
Page 33
... I/O lines with 5-V input and drive capability — Input threshold on external bus interface inputs switchable for 3.3-V or 5-V operation — 5-V A/D converter inputs — Operation at 80 MHz equivalent to 40-MHz bus speed Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.21 Chapter 1 Device Overview MC9S12XD-Family 33 ...
Page 34
... MC9S12XDP512RMV2. Availability of modules on other family members see Appendix E Derivative Differences. ATD Converter is routed to pins PAD00 - PAD15 on maskset M42E. See Converter (ATD10B16CV4) Block Description 34 Appendix E Derivative Differences Figure 1-2 shows blocks integrated on maskset M42E. The 16 channel 123. MC9S12XDP512 Data Sheet, Rev. 2.21 for Chapter 4 Analog-to-Digital Freescale Semiconductor ...
Page 35
... PC0 DATA7 PD7 DATA6 PD6 DATA5 PD5 DATA4 PD4 DATA3 PD3 DATA2 PD2 DATA1 PD1 DATA0 PD0 Freescale Semiconductor ATD0 AN0 4/2/1-Kbyte EEPROM AN1 AN2 AN3 Voltage Regulator AN4 AN5 AN6 AN7 CPU12X Enhanced Multilevel Interrupt Module Clock Periodic Interrupt COP Watchdog ...
Page 36
... KWP2 PP2 PWM3 KWP3 PP3 PWM4 KWP4 PP4 PP5 PWM5 KWP5 PWM6 KWP6 PP6 PWM7 KWP7 PP7 MISO KWH0 PH0 MOSI KWH1 PH1 SCK KWH2 PH2 SS KWH3 PH3 KWH4 PH4 PH5 KWH5 KWH6 PH6 KWH7 PH7 Freescale Semiconductor RH RL DDA SSA ...
Page 37
... Freescale Semiconductor Appendix E Derivative Differences Table 1-1 is not allocated to any module. Writing to these Table 1-2. Table 1-1. Device Register Memory Map Module ) PIM (port integration module ...
Page 38
... CAN3 (scalable CAN) PIM (port integration module) CAN4 (scalable CAN) Reserved ATD0 (analog-to-digital converter 10 bit 8-channel) Unimplemented Voltage regulator Unimplemented PWM (pulse-width modulator 8 channels) Unimplemented Periodic interrupt timer Unimplemented XGATE Unimplemented Unimplemented MC9S12XDP512 Data Sheet, Rev. 2.21 Size (Bytes 192 1024 Freescale Semiconductor ...
Page 39
... RAM 0x4000 Unpaged 16K FLASH 0x8000 16K FLASH window 0xC000 Unpaged 16K FLASH Reset Vectors 0xFFFF Figure 1-3. S12X CPU & BDM Global Address Mapping Freescale Semiconductor 0x00_0000 0x00_07FF RAM_LOW 0x0F_FFFF EPAGE RPAGE EEPROM_LOW 0x13_FFFF 0x1F_FFFF PPAGE 0x3F_FFFF FLASH_LOW 0x7F_FFFF MC9S12XDP512 Data Sheet, Rev ...
Page 40
... MC9S12XDP512 Data Sheet, Rev. 2.21 Figure 1-3) FLASHSIZE/ FLASH_LOW 512K 0x78_0000 512K 0x78_0000 512K 0x78_0000 128K 7E_0000 128K 7E_0000 128K 7E_0000 64K 7F_0000 128K 7E_0000 128K 7E_0000 Freescale Semiconductor ...
Page 41
... RAM 0x4000 Unpaged 16K FLASH 0x8000 16K FLASH window 0xC000 Unpaged 16K FLASH Reset Vectors 0xFFFF Figure 1-4. S12X CPU & BDM Global Address Mapping Freescale Semiconductor 0x00_0000 0x00_07FF RAM_LOW 0x0F_FFFF EPAGE RPAGE EEPROM_LOW 0x13_FFFF 0x1F_FFFF PPAGE 0x3F_FFFF 0x78_0000 FLASH0_LOW ...
Page 42
... EEPROMSIZE/ FLASHSIZE0/ EEPROM_LOW FLASH_LOW 4K 0x13_F000 0x79_FFFF 4K 0x13_F000 4K 0x13_F000 4K 0x13_F000 0x79_FFFF 4K 0x13_F000 2K 0x13_F800 MC9S12XDP512 Data Sheet, Rev. 2.21 Figure 1-4) FLASHSIZE1/ FLASH_HIGH 128K 256K 0x7C_0000 128K 128K 0x7E_0000 Freescale Semiconductor ...
Page 43
... XGATE Local Memory Map 0x0000 Registers 0x0800 FLASH RAM 0xFFFF Freescale Semiconductor Figure 1-5. GATE Global Address Mapping XGRAM_LOW XGFLASH_HIGH MC9S12XDP512 Data Sheet, Rev. 2.21 Chapter 1 Device Overview MC9S12XD-Family Global Memory Map 0x00_0000 Registers 0x00_07FF RAM 0x0F_FFFF 0x78_0800 FLASH 0x7F_FFFF 43 ...
Page 44
... Available Flah Memory 30K on all listed parts 44 Table 1-4. XGATE Resources (see XGRANMSIZE XGRAM_LOW 32K 0x0F_8000 20K 0x0F_B000 20K 0x0F_B000 32K 0x0F_8000 16K 0x0F_C000 14K 0x0F_C800 10K 0x0F_D800 16K 0x0F_C000 MC9S12XDP512 Data Sheet, Rev. 2.21 Figure 1-5) 1 XGFLASHSIZE XGFLASH_HIGH 30K 0x78_7FFF Freescale Semiconductor ...
Page 45
... XGATE Local Memory Map 0x0000 Registers 0x0800 RAM 0xFFFF Freescale Semiconductor Figure 1-6. XGATE Global Address Mapping MC9S12XDP512 Data Sheet, Rev. 2.21 Chapter 1 Device Overview MC9S12XD-Family Global Memory Map 0x00_0000 Registers 0x00_07FF XGRAM_LOW RAM 0x0F_FFFF 0x7F_FFFF 45 ...
Page 46
... Chapter 1 Device Overview MC9S12XD-Family Device 9S12XDG128 3S12XDG128 9S12XD128 9S12XD64 9S12XB128 9S12XA128 46 Table 1-5. XGATE Resources (see XGRAMSIZE 12K 12K 12K MC9S12XDP512 Data Sheet, Rev. 2.21 Figure 1-6) XGRAM_LOW 0x0F_D000 0x0F_D000 0x0F_E000 0x0F_F000 0x0F_E800 0x0F_D000 Freescale Semiconductor ...
Page 47
... This section describes signals that connect off-chip. It includes a pinout diagram, a table of signal properties, and detailed discussion of signals. 1.2.1 Device Pinout The MC9S12XD family of devices offers pin-compatible packaged devices to assist with system development and accommodate expansion of the application. Freescale Semiconductor Mask Set Number 0L15Y/1L15Y/0M23S 0L15Y/1L15Y/0M23S 0L15Y/1L15Y/0M23S 0L15Y/1L15Y/0M23S ...
Page 48
... Not all functions are shown in the following pinouts. Please refer to Table 1-7 on different family members refer to For pinout explanations of the different parts refer to explanations: 48 for package options. CAUTION for a complete description. For avalability of the modules Appendix E Derivative MC9S12XDP512 Data Sheet, Rev. 2.21 Differences. E.7 Pinout Freescale Semiconductor ...
Page 49
... ADDR3/PB3 ADDR4/PB4 36 Figure 1-7. MC9S12XD Family Pin Assignment 144-Pin LQFP Package Freescale Semiconductor MC9S12XD-Family 144-Pin LQFP Pins shown in BOLD-ITALICS are not available on the 112-Pin LQFP or the 80-Pin QFP package option Pins shown in BOLD are not available on the 80-Pin QFP package option MC9S12XDP512 Data Sheet, Rev ...
Page 50
... Pins shown in BOLD are not available on the 80-Pin QFP package option MC9S12XDP512 Data Sheet, Rev. 2.21 84 VRH 83 VDDA 82 PAD15/AN15 81 PAD07/AN07 80 PAD14/AN14 79 PAD06/AN06 78 PAD13/AN13 77 PAD05/AN05 76 PAD12/AN12 75 PAD04/AN04 74 PAD11/AN11 73 PAD03/AN03 72 PAD10/AN10 71 PAD02/AN02 70 PAD09/AN09 69 PAD01/AN01 68 PAD08/AN08 67 PAD00/AN00 66 VSS2 65 VDD2 64 PA7 63 PA6 62 PA5 61 PA4 60 PA3 59 PA2 58 PA1 57 PA0 Freescale Semiconductor ...
Page 51
... SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 MOSI1/PWM1/KWP1/PP1 MISO1/PWM0/KWP0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 VDD1 VSS1 IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD PB0 PB1 PB2 PB3 PB4 Figure 1-9. MC9S12XD Family Pin Assignments 80-Pin QFP Package Freescale Semiconductor MC9S12XD-Family 11 80-Pin QFP MC9S12XDP512 Data Sheet, Rev. 2.21 Chapter 1 Device Overview MC9S12XD-Family ...
Page 52
... While RESET Port E I/O, read enable, pin is low: down mode input, tag low input PUCR Up Port E I/O, bus clock output PUCR Up Port E I/O, low byte data strobe, EROMON control PUCR Up Port E I/O, read/write PUCR Up Port E Input, maskable interrupt Freescale Semiconductor ...
Page 53
... PJ0 KWJ0 RXD2 PK7 — — PK[5:4] — — PK7 EWAIT ROMCTL PK[6:4] ADDR ACC[2:0] [22:20] PK3 ADDR19 IQSTAT3 Freescale Semiconductor Pin Pin Power Name Name Supply Function 4 Function 5 — — V DDR TXD5 — V PERH/PPSH Disabled Port H I/O, interrupt DDR RXD5 — ...
Page 54
... Disabled Port P I/O, interrupt, channel PPSP 2 of PWM, SCK of SPI1 PERP/ Disabled Port P I/O, interrupt, channel PPSP 1 of PWM, MOSI of SPI1 PERP/ Disabled Port P I/O, interrupt, channel PPSP 0 of PWM, MISO2 of SPI1 PERS/ Up Port S I/ SPI0 PPSS PERS/ Up Port S I/O, SCK of SPI0 PPSS Freescale Semiconductor ...
Page 55
... The RESET pin is an active low bidirectional control signal. It acts as an input to initialize the MCU to a known start-up state output it is driven ;ow to indicate when any internal MCU reset source triggers. The RESET pin has an internal pullup device. Freescale Semiconductor Pin Pin ...
Page 56
... PAD[15:0] / AN[15:0] — Port AD Input Pins of ATD1 PAD[15:0] are general-purpose input or output pins and analog inputs AN[15:0] of the analog-to-digital converter ATD1. 56 NOTE in all applications DDPLL C S MCU R 0 XFC Figure 1-10. PLL Loop Filter Connections MC9S12XDP512 Data Sheet, Rev. 2.21 V DDPLL C P Freescale Semiconductor ...
Page 57
... PE7 is a general-purpose input or output pin. The XCLKS is an input signal which controls whether a crystal in combination with the internal loop controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock circuitry is used. Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.21 Chapter 1 Device Overview MC9S12XD-Family ...
Page 58
... The state of this pin is latched to the MODB bit at the rising edge of RESET. This pin is an input with a 58 EXTAL C 1 MCU Crystal or Ceramic Resonator XTAL Ceramic Resonator R S CMOS-Compatible EXTAL External Oscillator MCU XTAL Not Connected MC9S12XDP512 Data Sheet, Rev. 2.21 V SSPLL C 1 Crystal SSPLL Freescale Semiconductor ...
Page 59
... PE0 / XIRQ — Port E Input Pin 0 PE0 is a general-purpose input pin and the non-maskable interrupt request input that provides a means of applying asynchronous interrupt requests. This will wake up the MCU from stop or wait mode. Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.21 Chapter 1 Device Overview MC9S12XD-Family ...
Page 60
... PH1 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as master output (during master mode) or slave input pin (during slave mode) MOSI of the serial peripheral interface 1 (SPI1). 60 MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor ...
Page 61
... PJ0 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as the receive pin RXD of the serial communication interface 2 (SCI2).It can be configured to provide a chip-select output. Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.21 Chapter 1 Device Overview MC9S12XD-Family ...
Page 62
... PM5 is a general-purpose input or output pin. It can be configured as the transmit pin TXCAN of the scalable controller area network controllers (CAN0, CAN2, or CAN4). It can be configured as the serial clock pin SCK of the serial peripheral interface 0 (SPI0). 62 MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor ...
Page 63
... PP5 / KWP5 / PWM5 / MOSI2 — Port P I/O Pin 5 PP5 is a general-purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit stop or wait mode. It can be configured as pulse width modulator (PWM) channel 5 output. It can Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.21 Chapter 1 Device Overview MC9S12XD-Family ...
Page 64
... PS7 is a general-purpose input or output pin. It can be configured as the slave select pin SS of the serial peripheral interface 0 (SPI0). 1.2.3.61 PS6 / SCK0 — Port S I/O Pin 6 PS6 is a general-purpose input or output pin. It can be configured as the serial clock pin SCK of the serial peripheral interface 0 (SPI0). 64 MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor ...
Page 65
... External power and ground for I/O drivers. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded. Freescale Semiconductor NOTE , V ,V — ...
Page 66
... No load allowed except for bypass capacitors — Power and Ground Pins for I/O Drivers SSR1 SSR2 , V — Core Power Pins SS1 SS2 and V . Because fast signal transitions place high NOTE — Power Supply Pins for PLL NOTE MC9S12XDP512 Data Sheet, Rev. 2.21 REG Freescale Semiconductor ...
Page 67
... V 138 SSX1 V 26 DDX2 V 27 SSX2 V 82 DDR2 V 81 SSR2 V 107 DDA V 110 SSA V 109 RL V 108 DDPLL V 57 SSPLL Freescale Semiconductor Nominal 112-Pin 80-Pin Voltage LQFP QFP 13 2.5 V 14 107 77 5.0 V 106 N.A. N.A. 5.0 V N.A. N. N.A. N.A. 5 ...
Page 68
... CRG to all modules. CAN Modules Oscillator Clock Core Clock S12X XGATE 1-12, this system clocks are used throughout the MCU to drive the core, the MC9S12XDP512 Data Sheet, Rev. 2.21 IIC Modules ATD Modules PIT ECT PIM FLASH EEPROM Freescale Semiconductor ...
Page 69
... MODC signal during reset. The MODC bit in the MODE register shows the current operating mode and provide limited mode switching during operation. The state of the MODC signal is latched into this bit on the rising edge of RESET. Freescale Semiconductor CAUTION MC9S12XDP512 Data Sheet, Rev. 2.21 ...
Page 70
... Data Source EROMCTL X X Internal X 0 Emulation memory X 1 Internal Flash 0 X External application 1 X Internal Flash 0 X External application 1 0 Emulation memory 1 1 Internal Flash 0 X External application 1 X Internal Flash Table 1-10). For a detailed and V must be DD1,2 DDPLL Freescale Semiconductor 1 ...
Page 71
... The microcontroller features two main low-power modes. Consult the respective sections for information on the module behavior in system stop, system pseudo stop, and system wait mode. An important source of information about the clock system is the Clock and Reset Generator S12CRG section. Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.21 Chapter 1 Device Overview MC9S12XD-Family ...
Page 72
... Associated with each I-bit maskable service request is a configuration register. It selects if the service request is enabled, the service request priority level and whether the service request is handled either by the S12X CPU or by the XGATE module. 72 MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor ...
Page 73
... Vector base + $CA $65 Vector base + $C8 $64 Vector base + $C6 $63 Vector base + $C4 $62 Vector base + $C2 Vector base + $C0 $60 Freescale Semiconductor Interrupt Source 2 System reset or illegal access reset Clock monitor reset COP watchdog reset Unimplemented instruction trap SWI XIRQ IRQ Real time interrupt ...
Page 74
... CAN2TIER (TXEIE[2:0]) I bit CAN3RIER (WUPIE) I bit CAN3RIER (CSCIE, OVRIE) I bit CAN3RIER (RXFIE) I bit CAN3TIER (TXEIE[2:0]) I bit CAN4RIER (WUPIE) I bit CAN4RIER (CSCIE, OVRIE) I bit CAN4RIER (RXFIE) I bit CAN4TIER (TXEIE[2:0]) I bit PIEP (PIEP7-PIEP0) I bit PWMSDN (PWMIE) I bit SCI2CR2 (TIE, TCIE, RIE, ILIE) Freescale Semiconductor ...
Page 75
... Vector base + $60 — Vector base+ $12 to Vector base + $5E Vector base + $10 — bits vector address based 2 For detailed description of XGATE channel ID refer to XGATE Block Guide Freescale Semiconductor Interrupt Source 2 SCI3 Reserved SCI4 SCI5 Reserved IIC1 Bus Reserved Low-voltage interrupt (LVI) Autonomous periodical interrupt (API) ...
Page 76
... Table 1-13. Initial COP Rate Configuration NV[2:0] in CR[2:0] in COPCTL Register 000 001 010 011 100 101 110 111 Table 1-14. Initial WCOP Configuration NV[3] in COPCTL Register 1 0 MC9S12XDP512 Data Sheet, Rev. 2.21 111 110 101 100 011 010 001 000 WCOP Freescale Semiconductor ...
Page 77
... See Section Chapter 4, “Analog-to-Digital Converter (ATD10B16CV4) Block Description about the analog-to-digital converter module. When this section refers to freeze mode this is equivalent to active BDM mode. Freescale Semiconductor Table 1-15. ATD0 External Trigger Sources Connected Pulse width modulator channel 1 Pulse width modulator channel 3 Periodic interrupt timer hardware trigger0 PITTRIG[0] ...
Page 78
... Chapter 1 Device Overview MC9S12XD-Family 78 MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor ...
Page 79
... System reset generation from the following possible sources: — Power on reset — Low voltage reset — Illegal address reset — COP reset — Loss of clock reset — External pin reset • Real-time interrupt (RTI) Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.21 79 ...
Page 80
... Self clock mode should be used for safety purposes only. It provides reduced functionality to the MCU in case a loss of clock is causing severe system conditions. 80 MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor ...
Page 81
... CRG. S12X_MMC Voltage Regulator RESET Clock Monitor XCLKS Oscillator EXTAL XTAL XFC V DDPLL V SSPLL Freescale Semiconductor Illegal Address Reset Power on Reset Low Voltage Reset CRG Reset Generator CM fail Clock Quality OSCCLK Checker COP Registers PLLCLK Clock and Reset PLL Control Figure 2-1 ...
Page 82
... This section provides a detailed description of all registers accessible in the CRG. 82 — Operating and Ground Voltage Pins SSPLL ) and ground (V DDPLL C S MCU R S XFC Figure 2-2. PLL Loop Filter Connections MC9S12XDP512 Data Sheet, Rev. 2.21 ) for the PLL circuitry. This allows SSPLL V DDPLL C P Freescale Semiconductor DDPLL ...
Page 83
... CTCTL is intended for factory test purposes only. Register Address = Base Address + Address Offset, where the Base Address is defined at the MCU level and the Address Offset is defined at the module level. Freescale Semiconductor Table 2-1. CRG Memory Map Use CRG Synthesizer Register (SYNR) ...
Page 84
... Figure 2-3. S12CRGV6 Register Summary MC9S12XDP512 Data Sheet, Rev. 2. SYN3 SYN2 SYN1 REFDV3 REFDV2 REFDV1 LOCK TRACK SCMIF 0 0 SCMIE 0 PLLWAI RTIWAI FSTWKP PRE PCE RTR3 RTR2 RTR1 0 CR2 CR1 Bit 3 Bit 2 Bit 1 Freescale Semiconductor Bit 0 SYN0 REFDV0 0 SCM 0 COPWAI SCME RTR0 CR0 Bit 0 ...
Page 85
... Reset Unimplemented or Reserved Figure 2-5. CRG Reference Divider Register (REFDV) Read: Anytime Write: Anytime except when PLLSEL = 1 Write to this register initializes the lock detector bit and the track detector bit. Freescale Semiconductor SYNR + 1 ----------------------------------- - REFDV + 1 NOTE 5 4 SYN5 SYN4 0 0 Figure 2-4. CRG Synthesizer Register (SYNR) ...
Page 86
... Power on reset has not occurred. 1 Power on reset has occurred Figure 2-6. Reserved Register (CTFLG) NOTE 5 4 LOCK LVRF LOCKIF 2 0 Figure 2-7. CRG Flags Register (CRGFLG) Table 2-2. CRGFLG Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. TRACK SCMIF Freescale Semiconductor SCM 0 ...
Page 87
... Self Clock Mode Status Bit — SCM reflects the current clocking mode. Writes have no effect. SCM 0 MCU is operating normally with OSCCLK available. 1 MCU is operating in self clock mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK running at its minimum frequency f Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) Description . SCM MC9S12XDP512 Data Sheet, Rev ...
Page 88
... LOCK interrupt requests are disabled. 1 Interrupt will be requested whenever LOCKIF is set. 1 Self ClockMmode Interrupt Enable Bit SCMIE 0 SCM interrupt requests are disabled. 1 Interrupt will be requested whenever SCMIF is set LOCKIE Table 2-3. CRGINT Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. SCMIE Freescale Semiconductor ...
Page 89
... RTI stops and initializes the RTI dividers whenever the part goes into wait mode. 0 COP Stops in Wait Mode Bit COPWAI Normal modes: Write once Special modes: Write anytime 0 COP keeps running in wait mode. 1 COP stops and initializes the COP counter whenever the part goes into wait mode. Freescale Semiconductor Figure 2- PLLWAI ...
Page 90
... CRG will switch all system clocks to OSCCLK. The SCMIF flag will be set. See application examples in Figure 2-23 and Figure AUTO ACQ FSTWKP Table 2-5. PLLCTL Field Descriptions Description Checker”). The SCMIF flag will not be set. The system will remain in self-clock 2-24. MC9S12XDP512 Data Sheet, Rev. 2. PRE PCE SCME Freescale Semiconductor ...
Page 91
... Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to RTR[3:0] provide additional granularity.Table 2-7 register. The source clock for the RTI is OSCCLK. Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) Description RTR5 ...
Page 92
... Freescale Semiconductor 111 2x2 16 3x2 16 4x2 16 5x2 16 6x2 16 7x2 16 8x2 16 9x2 16 10x2 16 11x2 16 12x2 16 13x2 16 14x2 16 15x2 16 16x2 ...
Page 93
... Freescale Semiconductor RTR[6:4] = 010 011 100 (5x10 ) (10x10 ) (20x10 5x10 10x10 20x10 10x10 20x10 40x10 15x10 ...
Page 94
... Allows the COP and RTI to keep running in active BDM mode. 1 Stops the COP and RTI counters whenever the part is in active BDM mode WRTMASK Table 2-9. COPCTL Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. CR2 CR1 CR0 Table 2-10 shows the duration Freescale Semiconductor ...
Page 95
... Operation in emulation or special modes CR2 OSCCLK cycles are referenced from the previous COP time-out reset (writing 0x_55/0x_AA to the ARMCOP register) Freescale Semiconductor Description 24 2 cycles) in normal COP mode (Window COP mode disabled): Table 2-10. COP Watchdog Rates CR1 CR0 Cycles to Time-out ...
Page 96
... Writing to this register when in special test modes can alter the CRG’s functionality Reset Unimplemented or Reserved Read: always read 0x_80 except in special modes Write: only in special modes 96 NOTE Figure 2-13. Reserved Register (FORBYP) NOTE Figure 2-14. Reserved Register (CTCTL) MC9S12XDP512 Data Sheet, Rev. 2. Freescale Semiconductor ...
Page 97
... COP reset. Sequences of 0x_55 writes or sequences of 0x_AA writes are allowed. When the WCOP bit is set, 0x_55 and 0x_AA writes must be done in the last 25% of the selected time-out period; writing any value in the first 75% of the selected period will cause a COP reset. Freescale Semiconductor ...
Page 98
... REFDV <5:0> FEEDBACK REFERENCE PROGRAMMABLE DIVIDER LOOP PROGRAMMABLE DIVIDER SYN <5:0> Figure 2-16. PLL Functional Diagram MC9S12XDP512 Data Sheet, Rev. 2. LOCK LOCK DETECTOR V /V DDPLL SSPLL UP PDET PHASE CPUMP VCO DOWN DETECTOR V DDPLL LOOP FILTER XFC PIN Freescale Semiconductor . SCM PLLCLK ...
Page 99
... If the PLL is selected as the source for the system and core clocks and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev. 2.21 Figure 2-16 ...
Page 100
... WAIT(COPWAI), STOP(PSTP,PCE), COP ENABLE STOP Figure 2-17. System Clocks Generator MC9S12XDP512 Data Sheet, Rev. 2.21 , and is clear when trk , and is cleared Lock . ) before acq ) before selecting the PLLCLK al CORE CLOCK 2 CLOCK PHASE BUS CLOCK GENERATOR RTI COP OSCILLATOR CLOCK Freescale Semiconductor ...
Page 101
... Wake-up from full stop mode (exit full stop) • Clock monitor fail indication (CM fail) A time window of 50,000 VCO clock cycles 1. VCO clock cycles are generated by the PLL when running at minimum frequency f Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) Figure Figure 2-18. But note that a CPU cycle corresponds called check window ...
Page 102
... Figure 2-19. Check Window Example Figure 2-20. CM fail yes num = 0 Enter SCM Clock Monitor Reset Enter SCM num=num–1 yes no num > Switch to OSCCLK Exit SCM MC9S12XDP512 Data Sheet, Rev. 2.21 Figure 2- example. 49999 50000 no FSTWKP = 0 ? yes num = 0 no yes SCM active? yes no SCME=1 ? Freescale Semiconductor ...
Page 103
... Operating Modes 2.4.2.1 Normal Mode The CRG block behaves as described within this specification in all normal modes Clock Monitor Reset will always set the SCME bit to logical 1. Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) NOTE 1 handling the clock quality checker continues to SCM Section 2.4.1.5, “ ...
Page 104
... If the external clock frequency is not available due SCM NOTE PLLWAI RTIWAI Stopped — RTI — Stopped — — (Figure 2-21). Depending on the configuration, the CRG MC9S12XDP512 Data Sheet, Rev. 2.21 Section 2.4.1.4, “Clock Quality COPWAI — — Stopped Freescale Semiconductor ...
Page 105
... CPU Req’s Wait Mode. No PLLWAI=1 ? Yes Clear PLLSEL, Disable PLL due to external reset Freescale Semiconductor Enter Wait Mode Wait Mode left Exit Wait w. ext.RESET No Exit Wait w. CMRESET SCMIE=1 Generate SCM Interrupt (Wakeup from Wait) Wait Mode Continue w. Normal OP Figure 2-21. Wait Mode Entry/Exit Sequence MC9S12XDP512 Data Sheet, Rev ...
Page 106
... A complete timeout window check will be started when stop mode is left again. Wake-up from stop mode also depends on the setting of the PSTP bit. 106 MC9S12XDP512 Data Sheet, Rev. 2.21 (Section 2.4.1.4, “Clock Freescale Semiconductor ...
Page 107
... Scenario 2: OSCCLK does not recover prior to exiting wait mode. Clock failure --> SCMIF generates self clock mode wakeup interrupt. Freescale Semiconductor CRG Actions No action, clock loss not detected. CRG performs Clock Monitor Reset immediately – MCU remains in wait mode, – VREG enabled, – ...
Page 108
... Continue w. normal OP Figure 2-22. Stop Mode Entry/Exit Sequence MC9S12XDP512 Data Sheet, Rev. 2.21 Yes No CME=1 INT ? ? Yes Yes No CM fail ? Yes no SCME=1 ? Yes Exit Stop Mode No SCMIE=1 ? Yes Exit SCM=1 Stop Mode ? Yes Enter Enter SCM SCM Freescale Semiconductor No No ...
Page 109
... PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving stop mode. The software must set the PLLSEL bit again, in order to switch system and core clocks to the PLLCLK. Table 2-13 summarizes the outcome of a clock loss while in pseudo stop mode. Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) MC9S12XDP512 Data Sheet, Rev. 2.21 (Section 2.4.1.4, “Clock ...
Page 110
... SCMIF generates self clock mode wakeup interrupt. – Exit pseudo stop mode in SCM using PLL clock (f – Continue to perform a additional clock quality checks until OSCCLK is o.k. again. MC9S12XDP512 Data Sheet, Rev. 2.21 CRG Actions ) as system clock SCM ) as system clock SCM ) as system clock, SCM Freescale Semiconductor ...
Page 111
... PLLCLK. In full stop mode or self-clock mode caused by the fast wake-up feature, the clock monitor and the oscillator are disabled. Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) Checker”). After completing the clock quality check NOTE MC9S12XDP512 Data Sheet, Rev ...
Page 112
... Interrupt Interrupt Power Saving Oscillator Disabled Self-Clock Mode IRQ Service FSTWKP=0 SCMIE=1 OSC Startup Self-Clock Mode MC9S12XDP512 Data Sheet, Rev. 2.21 IRQ Service IRQ Service STOP Interrupt Freq. Critical Freq. Uncritical Instructions Instr. Possible SCM Interrupt Clock Quality Check Freescale Semiconductor ...
Page 113
... After 128 + n SYSCLK cycles the RESET pin is released. The reset generator of the CRG waits for additional 64 SYSCLK cycles and then samples the RESET pin to determine the originating source. Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) Section 2.3, “Memory Map and Register Table 2-14. Refer to MCU specifi ...
Page 114
... With n being Possibly min 3 / max 6 SYSCLK cycles depending not on internal running synchronization delay Figure 2-25. RESET Timing MC9S12XDP512 Data Sheet, Rev. 2.21 Vector Fetch Clock Monitor Reset COP Reset with rise of RESET pin ) ) ( ( 64 cycles Possibly RESET driven low externally Freescale Semiconductor ...
Page 115
... Figure 2-27 show the power-up sequence for cases when the RESET pin is tied to V and when the RESET pin is held low. Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) to the MCU has reached a certain level and asserts power DD MC9S12XDP512 Data Sheet, Rev. 2.21 Section 2 ...
Page 116
... SYSCLK 64 SYSCLK ) ( Figure 2-27. RESET Pin Held Low Externally Table 2-16. CRG Interrupt Vectors CCR Mask I bit I bit CRGINT (LOCKIE) I bit CRGINT (SCMIE) MC9S12XDP512 Data Sheet, Rev. 2.21 Table 2-16. Refer to MCU specification for Local Enable CRGINT (RTIE) Freescale Semiconductor ...
Page 117
... SCM interrupts are locally disabled by setting the SCMIE bit to 0. The SCM interrupt flag (SCMIF) is set to1 when the SCM condition has changed, and is cleared writing the SCMIF bit. Freescale Semiconductor Chapter 2 Clocks and Reset Generator (S12CRGV6) Section 2.4.1.4, “Clock Quality MC9S12XDP512 Data Sheet, Rev. 2.21 Checker” ...
Page 118
... Chapter 2 Clocks and Reset Generator (S12CRGV6) 118 MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor ...
Page 119
... Modes of Operation Two modes of operation exist: 1. Loop controlled Pierce oscillator 2. External square wave mode featuring also full swing Pierce without internal feedback resistor Freescale Semiconductor supply rail (2.5 V nominal) and require the minimum number DDPLL MC9S12XDP512 Data Sheet, Rev. 2.21 119 ...
Page 120
... XTAL is the output of the crystal oscillator amplifier. The MCU internal system clock is derived from the 120 Monitor_Failure Clock Monitor Gain Control V DDPLL Rf Figure 3-1. XOSC Block Diagram — Operating and Ground Voltage Pins SSPLL ) and ground (V DDPLL MC9S12XDP512 Data Sheet, Rev. 2.21 OSCCLK = 2.5 V XTAL ) for the XOSC circuitry. This SSPLL Freescale Semiconductor ...
Page 121
... EXTAL MCU XTAL * R can be zero (shorted) when use with higher frequency crystals. s Refer to manufacturer’s data. Figure 3-3. Full Swing Pierce Oscillator Connections (XCLKS = 0) Figure 3-4. External Clock Connections (XCLKS = 0) Freescale Semiconductor NOTE EXTAL C1 MCU Crystal or Ceramic Resonator XTAL C2 NOTE ...
Page 122
... CME control bit, described in the CRG block description chapter. 122 Table 3-1. Clock Selection Based on XCLKS Description Loop controlled Pierce oscillator selected Full swing Pierce oscillator/external clock selected power supply pins. SSPLL MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor ...
Page 123
... During wait mode, XOSC is not impacted. 3.4.4 Stop Mode Operation XOSC is placed in a static state when the part is in stop mode except when pseudo-stop mode is enabled. During pseudo-stop mode, XOSC is not impacted. Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.21 Chapter 3 Pierce Oscillator (S12XOSCLCPV1) 123 ...
Page 124
... Chapter 3 Pierce Oscillator (S12XOSCLCPV1) 124 MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor ...
Page 125
... Modes of Operation There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels. 4.1.3 Block Diagram Refer to Figure 4-1 for a block diagram of the ATD0B16C block. Freescale Semiconductor chapter for ATD accuracy. MC9S12XDP512 Data Sheet, Rev. 2.21 125 ...
Page 126
... DAC Sample & Hold 1 Analog MUX Figure 4-1. ATD10B16C Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.21 ATD10B16C Sequence Complete Interrupt Results ATD 0 ATD 1 ATD 2 ATD 3 ATD 4 ATD 5 ATD 6 ATD 7 ATD 8 ATD 9 ATD 10 ATD 11 ATD 12 ATD 13 ATD 14 ATD Comparator Freescale Semiconductor ...
Page 127
... This section provides a detailed description of all registers accessible in the ATD10B16C. 4.3.1 Module Memory Map Table 4-1 gives an overview of all ATD10B16C registers Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description chapter for availability and connectivity of these inputs. is the low reference voltage for ATD conversion. RL MC9S12XDP512 Data Sheet, Rev ...
Page 128
... ATD Result Register 14 (ATDDR14H, ATDDR14L) ATD Result Register 15 (ATDDR15H, ATDDR15L) NOTE MC9S12XDP512 Data Sheet, Rev. 2.21 Access R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Freescale Semiconductor ...
Page 129
... ATDSTAT0 W 0x0007 R Unimplemented W 0x0008 R ATDTEST0 W 0x0009 R ATDTEST1 W 0x000A R CCF15 ATDSTAT2 W 0x000B R CCF7 ATDSTAT1 W 0x000C R IEN15 ATDDIEN0 W Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description AFFC AWAI ETRIGLE S8C S4C S2C SMP1 SMP0 PRS4 DSGN SCAN MULT 0 ETORF FIFOR Unimplemented Unimplemented CCF14 ...
Page 130
... WRAP3 0 0 Table 4-2. ATDCTL0 Field Descriptions Description Table MC9S12XDP512 Data Sheet, Rev. 2. IEN3 IEN2 IEN1 PTAD11 PTAD10 PTAD9 PTAD3 PTAD2 PTAD1 BIT 5 BIT 4 BIT 3 BIT 3 BIT 2 BIT Unaffected WRAP2 WRAP1 4-3. Freescale Semiconductor Bit 0 IEN0 PTAD8 PTAD0 BIT 2 BIT WRAP0 1 ...
Page 131
... The coding is summarized in 3:0 External Trigger Channel Select — These bits select one of the AD channels or one of the ETRIG[3:0] inputs ETRIGCH[3:0] as source for the external trigger. The coding is summarized in Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Multiple Channel Conversions WRAP1 WRAP0 ...
Page 132
... ETRIGCH2 ETRIGCH1 ETRIGCH0 MC9S12XDP512 Data Sheet, Rev. 2.21 External Trigger Source AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 1 ETRIG0 1 ETRIG1 1 ETRIG2 1 ETRIG3 Reserved Reserved Freescale Semiconductor ...
Page 133
... ATD Interrupt will be requested whenever ASCIF = 1 is set. 0 ATD Sequence Complete Interrupt Flag — If ASCIE = 1 the ASCIF flag equals the SCF flag (see ASCIF Section 4.3.2.7, “ATD Status Register ATD interrupt occurred 1 ATD sequence complete interrupt pending Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description AWAI ETRIGLE ...
Page 134
... Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description ETRIGLE 134 Table 4-7. External Trigger Configurations ETRIGP External Trigger Sensitivity 0 Falling Edge 1 Ring Edge 0 Low Level 1 High Level MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor ...
Page 135
... At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family. 3 Conversion Sequence Length — This bit controls the number of conversions per sequence. S1C all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 Family. Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description S4C S2C ...
Page 136
... Table 4-9. Conversion Sequence Length Coding S8C 136 Description Table 4-10. Leakage onto the storage node and comparator reference capacitors Number of Conversions S4C S2C S1C per Sequence MC9S12XDP512 Data Sheet, Rev. 2. Freescale Semiconductor ...
Page 137
... Table 4-10. ATD Behavior in Freeze Mode (Breakpoint) FRZ1 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description FRZ0 Behavior in Freeze Mode 0 Continue conversion 1 Reserved 0 Finish current conversion, then freeze 1 Freeze Immediately MC9S12XDP512 Data Sheet, Rev. 2.21 137 ...
Page 138
... Table 4-12. Sample Time Select SMP0 Length of 2nd Phase of Sample Time 0 2 A/D conversion clock periods 1 4 A/D conversion clock periods 0 8 A/D conversion clock periods 1 16 A/D conversion clock periods MC9S12XDP512 Data Sheet, Rev. 2. PRS2 PRS1 Freescale Semiconductor 0 PRS0 1 ...
Page 139
... Maximum ATD conversion clock frequency is 2 MHz. The maximum allowed bus clock frequency is shown in this column. 2 Minimum ATD conversion clock frequency is 500 kHz. The minimum allowed bus clock frequency is shown in this column. Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-13. Clock Prescaler Values Total Divisor Max. Bus Clock ...
Page 140
... AN0 (channel 0. 0 Sample only one channel 1 Sample across several channels 140 SCAN MULT Table 4-14. ATDCTL5 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. for details. Freescale Semiconductor ...
Page 141
... Volts 5.100 5.080 2.580 2.560 2.540 0.020 0.000 Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Description Table 4-17 lists the coding used to select the various analog input Table 4-15. Available Result Data Formats. DSGN Description and Bus Bit Mapping 0 8-bit / left justifi ...
Page 142
... Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-17. Analog Input Channel Select Coding 142 MC9S12XDP512 Data Sheet, Rev. 2.21 Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 Freescale Semiconductor ...
Page 143
... Write “1” to ETORF • Write to ATDCTL0,1,2,3,4 (a conversion sequence is aborted) • Write to ATDCTL5 (a new conversion sequence is started External trigger over run error has occurred 1 External trigger over run error has occurred Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description CC3 ...
Page 144
... If in FIFO mode (FIFO = 1) the register counter is not initialized. The conversion counters wraps around when its maximum value is reached. Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the conversion counter even if FIFO=1. 144 Description MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor ...
Page 145
... Writing to this register when in special modes can alter functionality. Field 0 Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using SC CC, CB, and CA of ATDCTL5. 0 Special channel conversions disabled 1 Special channel conversions enabled Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Figure 4-10 ...
Page 146
... Conversion number x not completed 1 Conversion number x has completed, result ready in ATDDRx 146 Table 4-20. Special Channel Select Coding CCF13 CCF12 CCF11 0 0 Table 4-21. ATDSTAT2 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2.21 CA Analog Input Channel X Reserved Reserved X Reserved CCF10 CCF9 Freescale Semiconductor 0 CCF8 0 ...
Page 147
... If AFFC = 1 and read of result register ATDDRx In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing by methods will be overwritten by the set. Conversion number x not completed Conversion number x has completed, result ready in ATDDRx Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description ...
Page 148
... IEN13 IEN12 IEN11 Table 4-23. ATDDIEN0 Field Descriptions Description IEN5 IEN4 IEN3 Table 4-24. ATDDIEN1 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. IEN10 IEN9 IEN8 IEN2 IEN1 IEN0 Freescale Semiconductor ...
Page 149
... ANx pin (signal potentials not meeting V If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns a “1”. Reset sets all PORTAD0 bits to “1”. Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 5 4 ...
Page 150
... Reset sets all PORTAD1 bits to “1”. 150 5 4 PTAD5 PTAD4 PTAD3 1 1 AN5 AN4 Figure 4-17. Port Data Register 1 (PORTAD1) Table 4-26. PORTAD1 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. PTAD2 PTAD1 AN3 AN2 AN1 specifications will have an indeterminate value)). IH Freescale Semiconductor 0 PTAD0 1 AN0 ...
Page 151
... Figure 4-18. Left Justified, ATD Conversion Result Register x, High Byte (ATDDRxH (10-BIT) BIT 1 BIT 0 R (8-BIT Reset Unimplemented or Reserved Figure 4-19. Left Justified, ATD Conversion Result Register x, Low Byte (ATDDRxL) Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description BIT 7 BIT 6 BIT 5 BIT 5 BIT 4 BIT ...
Page 152
... The input analog signals are unipolar and must fall within the potential range of V 152 BIT 5 BIT 4 BIT 3 BIT 5 BIT 4 BIT allow to isolate noise of other MCU circuitry from the analog sub-block. MC9S12XDP512 Data Sheet, Rev. 2. BIT 9 MSB BIT 2 BIT 1 BIT 2 BIT VDDA. SSA Freescale Semiconductor 0 BIT BIT 0 BIT 0 0 ...
Page 153
... During a conversion, if additional active edges are detected the overrun error flag ETORF is set. Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description Table 4-27 gives a brief description of the different Table 4-27. External Trigger Control Bits SCAN 0 Ignores external trigger. Performs one conversion sequence and stops. ...
Page 154
... In freeze mode, the ATD10B16C will behave according to the logical values of the FRZ1 and FRZ0 bits. This is useful for debugging and emulation. The reset value for the ADPU bit is zero. Therefore, when this module is reset reset into the power down state. 154 NOTE MC9S12XDP512 Data Sheet, Rev. 2.21 before initiating a new ATD SR Freescale Semiconductor ...
Page 155
... Interrupt Source Sequence Complete Interrupt See Section 4.3.2, “Register Descriptions,” Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description which details the registers and their bit fields. Table 4-28. Refer to MCU specification for related Table 4-28. ATD Interrupt Vectors ...
Page 156
... Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 156 MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor ...
Page 157
... Freescale Semiconductor Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description MC9S12XDP512 Data Sheet, Rev. 2.21 157 ...
Page 158
... Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description 158 MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor ...
Page 159
... Configurable location for channel wrap around (when converting multiple channels in a sequence). 5.1.2 Modes of Operation 5.1.2.1 Conversion Modes There is software programmable selection between performing single or continuous conversion on a single channel or multiple channels. Freescale Semiconductor MC9S12XDP512 Data Sheet, Rev. 2.21 159 ...
Page 160
... V RH 5.2.4 V and V DDA SSA These pins are the power supplies for the analog circuitry of the ATD block. 160 is the low reference voltage for ATD conversion. RL — Power Supply Pins MC9S12XDP512 Data Sheet, Rev. 2.21 before initiating a new ATD SR Freescale Semiconductor ...
Page 161
... ATDCTL1 V DDA V SSA AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) ATD clock Clock Prescaler Trigger Mode and Mux Timing Control ATDDIEN PORTAD Successive Approximation Register (SAR) and DAC Sample & Hold 1 Analog MUX Figure 5-1 ...
Page 162
... S4C S2C SMP1 SMP0 PRS4 DSGN SCAN MULT 0 ETORF FIFOR Unimplemented or Reserved MC9S12XDP512 Data Sheet, Rev. 2. WRAP2 WRAP1 0 ETRIGCH2 ETRIGCH1 ETRIGCH0 ETRIGP ETRIGE ASCIE S1C FIFO FRZ1 PRS3 PRS2 PRS1 CC2 CC1 Freescale Semiconductor Bit 0 WRAP0 ASCIF FRZ0 PRS0 CA CC0 U SC ...
Page 163
... BIT 7 MSB 8-BIT W ATDDR2L 10-BIT BIT 1 U 8-BIT W ATDDR3H 10-BIT BIT 9 MSB BIT 7 MSB 8-BIT W Figure 5-2. ATD Register Summary (Sheet Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2 CCF6 CCF5 CCF4 IEN6 IEN5 IEN4 PTAD6 PTAD5 PTAD4 Left Justified Result Data Section 5.3.2.13, “ ...
Page 164
... BIT 5 BIT 4 BIT 3 BIT 3 BIT 2 BIT BIT 5 BIT 4 BIT 3 BIT 3 BIT 2 BIT BIT 5 BIT 4 BIT 3 BIT 3 BIT 2 BIT BIT 9 MSB BIT 3 BIT 2 BIT 1 BIT 3 BIT 2 BIT 1 Freescale Semiconductor Bit BIT 2 BIT BIT 2 BIT BIT 2 BIT BIT 2 BIT BIT 8 0 BIT 0 BIT 0 ...
Page 165
... ATDD45H 10-BIT 0 0 8-BIT W ATDD45L 10-BIT BIT 7 BIT 7 MSB 8-BIT W ATDD46H 10-BIT 0 0 8-BIT W ATDDR6L 10-BIT BIT 7 BIT 7 MSB 8-BIT W Figure 5-2. ATD Register Summary (Sheet Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2 BIT 6 BIT 5 BIT 4 BIT 6 BIT 5 BIT BIT 6 BIT 5 BIT 4 ...
Page 166
... Multiple Channel Conversions (MULT = 1) WRAP1 WRAP0 Wrap Around to AN0 after Converting MC9S12XDP512 Data Sheet, Rev. 2. BIT 9 MSB BIT 3 BIT 2 BIT 1 BIT 3 BIT 2 BIT WRAP2 WRAP1 Table 5-2. Reserved AN1 AN2 AN3 AN4 AN5 AN6 AN7 Freescale Semiconductor Bit 0 BIT 8 0 BIT 0 BIT 0 0 WRAP0 1 ...
Page 167
... Only if ETRIG3–0 input option is available (see device overview chapter), else ETRISEL is ignored, that means external trigger source is still on one of the AD channels selected by ETRIGCH2–0 Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2 Table 5-3. ATDCTL1 Field Descriptions Description Table 5-4. ETRIGCH1 ETRIGCH0 ...
Page 168
... Note: If using one of the AD channel as external trigger (ETRIGSEL = 0) the conversion results for this channel have no meaning while external trigger mode is enabled. 168 AWAI ETRIGLE ETRIGP Table 5-5. ATDCTL2 Field Descriptions Description Table 5-4. If external trigger source is one of the AD channels, the digital MC9S12XDP512 Data Sheet, Rev. 2. ASCIF ETRIGE ASCIE Table 5-6 for Freescale Semiconductor ...
Page 169
... S8C, S4C, all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity to HC12 S2C, S1C Family. Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) Description (ATDSTAT0)”), else ASCIF reads zero. Writes have no effect. Table 5-6. External Trigger Configurations ...
Page 170
... Table 5-9. Leakage onto the storage node and comparator reference capacitors may S4C S2C S1C FRZ0 Behavior in Freeze Mode 0 Continue conversion 1 0 Finish current conversion, then freeze 1 Freeze Immediately MC9S12XDP512 Data Sheet, Rev. 2.21 Number of Conversions per Sequence Reserved Freescale Semiconductor ...
Page 171
... Note: The maximum ATD conversion clock frequency is half the bus clock. The default (after reset) prescaler value is 5 which results in a default ATD conversion clock frequency that is bus clock divided by 12. Table 5-12 illustrates the divide-by operation and the appropriate range of the bus clock. SMP1 Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2 SMP0 PRS4 PRS3 0 0 Table 5-10 ...
Page 172
... MC9S12XDP512 Data Sheet, Rev. 2. Min. Bus Clock 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz 9 MHz 10 MHz 11 MHz 12 MHz 13 MHz 14 MHz 15 MHz 16 MHz 17 MHz 18 MHz 19 MHz 20 MHz 21 MHz 22 MHz 23 MHz 24 MHz 25 MHz 26 MHz 27 MHz 28 MHz 29 MHz 30 MHz 31 MHz 32 MHz Freescale Semiconductor ...
Page 173
... In the case of multi-channel scans (MULT = 1), this selection code represents the first channel to be examined in the conversion sequence. Subsequent channels are determined by incrementing channel selection code; selection codes that reach the maximum value wrap around to the minimum value. Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) 5 ...
Page 174
... MC9S12XDP512 Data Sheet, Rev. 2.21 Signed Unsigned 10-Bit 10-Bit Codes Codes 7FC0 FFC0 7F00 FF00 7E00 FE00 0100 8100 0000 8000 FF00 7F00 8100 0100 8000 0000 Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Freescale Semiconductor ...
Page 175
... If in FIFO mode (FIFO = 1) the register counter is not initialized. The conversion counters wraps around when its maximum value is reached. Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0) clears the conversion counter even if FIFO=1. Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2 ...
Page 176
... Figure 5-10. Reserved Register (ATDTEST0) NOTE Figure 5-11. ATD Test Register 1 (ATDTEST1) Table 5-18. ATDTEST1 Field Descriptions Description Table 5-19 lists the coding. Table 5-19. Special Channel Select Coding MC9S12XDP512 Data Sheet, Rev. 2. Analog Input Channel Reserved Reserved Freescale Semiconductor ...
Page 177
... C) If AFFC=1 and read of result register ATDDRx In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing by methods will be overwritten by the set. 0 Conversion number x not completed 1 Conversion number x has completed, result ready in ATDDRx Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2 ...
Page 178
... PTAD5 PTAD4 PTAD3 1 1 AN5 AN4 AN3 Figure 5-14. Port Data Register (PORTAD) Table 5-22. PORTAD Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. IEN2 IEN1 PTAD2 PTAD1 AN2 AN1 or V specifications will have Freescale Semiconductor 0 IEN0 0 0 PTAD0 1 AN0 ...
Page 179
... Figure 5-17. Right Justified, ATD Conversion Result Register, High Byte (ATDDRxH BIT 7 BIT 6 R BIT 7 MSB BIT 6 W Reset Unimplemented or Reserved Figure 5-18. Right Justified, ATD Conversion Result Register, Low Byte (ATDDRxL) Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2 BIT 7 BIT 6 BIT 5 BIT 5 BIT 4 BIT ...
Page 180
... The power down (ADPU) bit must be set to disable both the digital clocks and the analog power consumption. Only analog input signals within the potential range non-railed digital output codes. 180 allow to isolate noise of other MCU circuitry from the analog sub-block MC9S12XDP512 Data Sheet, Rev. 2. SSA DDA (A/D reference potentials) will result RH Freescale Semiconductor . ...
Page 181
... If the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion sequence, this does not constitute an overrun; therefore, the flag is not set. If the trigger is left asserted in level mode while a sequence is completing, another sequence will be triggered immediately. Freescale Semiconductor Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2) Table 5-23 gives a brief description of the different Table 5-23 ...
Page 182
... See register descriptions for further details. 182 Table 5-24. Refer to the device overview chapter for related Table 5-24. ATD Interrupt Vectors CCR Mask I bit ASCIE in ATDCTL2 interrupt MC9S12XDP512 Data Sheet, Rev. 2.21 Definition”), which details the registers Local Enable Freescale Semiconductor ...
Page 183
... A 7-bit identifier associated with an XGATE channel. In S12X designs valid Channel IDs range from $78 to $09. XGATE Channel Interrupt An S12X_CPU interrupt that is triggered by a code sequence running on the XGATE module. XGATE Software Channel Freescale Semiconductor Core”) (Section 6.4.4, “Semaphores”) “Interrupts”) Mode” ...
Page 184
... There are four run modes on S12X devices. • Run mode, wait mode, stop mode The XGATE is able to operate in all of these three system modes. Clock activity will be automatically stopped when the XGATE module is idle. • Freeze mode (BDM active) 184 MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor ...
Page 185
... XGATE. Peripheral Interrupts XGATE Software Triggers Peripherals 6.2 External Signal Description The XGATE module has no external pins. Freescale Semiconductor S12X_INT Interrupt Flags Semaphores RISC Core Software Triggers S12X_MMC Figure 6-1. XGATE Block Diagram MC9S12XDP512 Data Sheet, Rev. 2.21 Chapter 6 XGATE (S12XGATEV2) (XGMCTL)” ...
Page 186
... Reserved R W Reserved R W XGVBR Unimplemented or Reserved Figure 6-2. XGATE Register Summary (Sheet 186 Figure XGE XGFRZ XGDBG XGSS XG XG XGIEM SWEIFM FACTM 0 XGVBR[15:1] MC9S12XDP512 Data Sheet, Rev. 2.21 6-2.The address listed for each register FACT SWEIF XGCHID[6:0] Freescale Semiconductor 0 XGIE 0 ...
Page 187
... XGIF_1F XGIF_1E XGIF_1D XGIF_1C XGIF_1B XGIF_1A XGIF_19 XGIF_18 XGF _17 XGIF_16 XGIF_15 XGIF_14 XGIF_13 XGIF_12 XGIF_11 XGIF_10 XGIF R XGIF_0F XGIF_0E XGIF_0D XGIF_0C XGIF_0B XGIF_0A XGIF_09 W = Unimplemented or Reserved Figure 6-2. XGATE Register Summary (Sheet Freescale Semiconductor 124 123 122 121 120 119 ...
Page 188
... R W XGR2 R W XGR3 R W XGR4 R W XGR5 R W XGR6 R W XGR7 Unimplemented or Reserved Figure 6-2. XGATE Register Summary (Sheet 188 XGPC XGR1 XGR2 XGR3 XGR4 XGR5 XGR6 XGR7 MC9S12XDP512 Data Sheet, Rev. 2. XGSWT[7:0] XGSEM[7: XGN XGZ XGV XGC Freescale Semiconductor 0 ...
Page 189
... XGSS Mask — This bit controls the write access to the XGSS bit. The XGSS bit can only be set or cleared if a XGSSM "1" is written to the XGSSM bit in the same register access. Read: This bit will always read "0". Write: 0 Disable write access to the XGSS in the same bus cycle 1 Enable write access to the XGSS in the same bus cycle Freescale Semiconductor ...
Page 190
... RISC core is not in Debug Mode 1 RISC core is in Debug Mode Write: 0 Leave Debug Mode 1 Enter Debug Mode Note: Freeze Mode and Software Error Interrupts have no effect on the XGDBG bit. 190 Description MC9S12XDP512 Data Sheet, Rev. 2.21 Section 6.6, “Debug Mode”). Freescale Semiconductor ...
Page 191
... Read: 0 All XGATE interrupts disabled 1 All XGATE interrupts enabled Write: 0 Disable all XGATE interrupts 1 Enable all XGATE interrupts Freescale Semiconductor Description Section 6.4.5, “Software Error MC9S12XDP512 Data Sheet, Rev. 2.21 Chapter 6 XGATE (S12XGATEV2) Detection”). The RISC core is stopped while 191 ...
Page 192
... XGATE channel that is currently Section 6.6.1, “Debug Features”). 5 4 XGCHID[6: Table 6-2. XGCHID Field Descriptions Description (Figure 6-5 and Figure 6-6) determines the location of the XGATE vector XGVBR[15: Table 6-3. XGVBR Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. Freescale Semiconductor ...
Page 193
... XGIF_0F XGIF_0E XGIF_0D XGIF_0C XGIF_0B XGIF_0A XGIF_09 W Reset Unimplemented or Reserved Figure 6-6. XGATE Channel Interrupt Flag Vector (XGIF) Read: Anytime Write: Anytime Freescale Semiconductor 6-6) provides access to the interrupt flags bits of each channel. Each flag 123 122 121 120 119 XGIF_78 ...
Page 194
... Suggested Mnemonics for accessing the interrupt flag vector on a word basis are: XGIF_7F_70 (XGIF[127:112]), XGIF_6F_60 (XGIF[111:96]), XGIF_5F_50 (XGIF[95:80]), XGIF_4F_40 (XGIF[79:64]), XGIF_3F_30 (XGIF[63:48]), XGIF_2F_20 (XGIF[47:32]), XGIF_1F_10 (XGIF[31:16]), XGIF_0F_00 (XGIF[15:0]) 194 Table 6-4. XGIV Field Descriptions Description NOTE MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor ...
Page 195
... The XGATE channel IDs that are associated with the eight software triggers are determined on chip integration level. (see Section “Interrupts” of the Soc Guide) XGATE software triggers work like any peripheral interrupt. They can be used as XGATE requests as well as S12X_CPU interrupts. The target of the software trigger must be selected in the S12X_INT module. Freescale Semiconductor ...
Page 196
... Semaphore is unlocked or locked by the RISC core 1 Semaphore is locked by the S12X_CPU Write: 0 Clear semaphore if it was locked by the S12X_CPU 1 Attempt to lock semaphore by the S12X_CPU 196 for details “Semaphores”) Table 6-6. XGSEM Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. XGSEM[7: Freescale Semiconductor ...
Page 197
... XGN 2 Zero Flag — The RISC core’s Zero flag XGZ 1 Overflow Flag — The RISC core’s Overflow flag XGV 0 Carry Flag — The RISC core’s Carry flag XGC Freescale Semiconductor XGN Table 6-7. XGCCR Field Descriptions Description MC9S12XDP512 Data Sheet, Rev ...
Page 198
... Write: In debug mode if unsecured Field 15–0 XGATE Register 1 — The RISC core’s register 1 XGR1[15:0] 198 XGPC Figure 6-11. Table 6-8. XGPC Field Descriptions Description XGR1 Figure 6-12. XGATE Register 1 (XGR1) Table 6-9. XGR1 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. Freescale Semiconductor ...
Page 199
... RISC core’s register Reset Read: In debug mode if unsecured Write: In debug mode if unsecured Field 15–0 XGATE Register 3 — The RISC core’s register 3 XGR3[15:0] Freescale Semiconductor XGR2 Figure 6-13. XGATE Register 2 (XGR2) Table 6-10. XGR2 Field Descriptions Description ...
Page 200
... XGATE Register 5 — The RISC core’s register 5 XGR5[15:0] 200 XGR4 Figure 6-15. XGATE Register 4 (XGR4) Table 6-12. XGR4 Field Descriptions Description XGR5 Figure 6-16. XGATE Register 5 (XGR5) Table 6-13. XGR5 Field Descriptions Description MC9S12XDP512 Data Sheet, Rev. 2. Freescale Semiconductor ...