IC M16C/62P MCU ROMLESS 100QFP

M30626SPFP#U5C

Manufacturer Part NumberM30626SPFP#U5C
DescriptionIC M16C/62P MCU ROMLESS 100QFP
ManufacturerRenesas Electronics America
SeriesM16C™ M16C/60
M30626SPFP#U5C datasheet
 


Specifications of M30626SPFP#U5C

Core ProcessorM16C/60Core Size16-Bit
Speed24MHzConnectivityI²C, IEBus, UART/USART
PeripheralsDMA, WDTNumber Of I /o50
Program Memory TypeROMlessRam Size31K x 8
Voltage - Supply (vcc/vdd)2.7 V ~ 5.5 VData ConvertersA/D 26x10b; D/A 2x8b
Oscillator TypeInternalOperating Temperature-20°C ~ 85°C
Package / Case100-QFPFor Use With867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
Program Memory Size-  
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To our customers,
Old Company Name in Catalogs and Other Documents
st
On April 1
, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website:
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
http://www.renesas.com
st
April 1
, 2010
Renesas Electronics Corporation

M30626SPFP#U5C Summary of contents

  • Page 1

    To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...

  • Page 2

    All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...

  • Page 3

    M16C/62P Group 16 (M16C/62P, M16C/62PT) Hardware Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject ...

  • Page 4

    Keep safety first in your circuit designs! Renesas Technology Corp. puts the maximum effort into making semiconductor products 1. better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...

  • Page 5

    How to Use This Manual 1. Introduction This hardware manual provides detailed information on the M16C/62P Group (M16C/62P, M16C/62PT) of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, ...

  • Page 6

    M16C Family Documents The following documents were prepared for the M16C family. Document Short Sheet Data Sheet Hardware Manual Software Manual Application Note RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document, NOTES: 1. Before ...

  • Page 7

    SFR Page Reference 1. Overview 1.1 Applications .................................................................................................1 1.2 Performance Outline ...................................................................................2 1.3 Block Diagram .............................................................................................5 1.4 Product List .................................................................................................7 1.5 Pin Configuration.......................................................................................14 1.6 Pin Description ..........................................................................................25 2. Central Processing Unit (CPU) 2.1 Data Registers (R0, R1, R2 and R3).........................................................30 ...

  • Page 8

    Brown-out Detection Reset (Hardware Reset 2) .......................................42 5.3 Software Reset..........................................................................................43 5.4 Watchdog Timer Reset.............................................................................43 5.5 Oscillation Stop Detection Reset...............................................................43 5.6 Internal Space ...........................................................................................44 6. Voltage Detection Circuit 6.1 Low Voltage Detection Interrupt ................................................................49 6.2 Limitations on Exiting Stop Mode ...

  • Page 9

    Clock Generation Circuit 10.1 Types of the Clock Generation Circuit.......................................................82 10.1.1 Main Clock..........................................................................................89 10.1.2 Sub Clock ...........................................................................................90 10.1.3 On-chip Oscillator Clock .....................................................................91 10.1.4 PLL Clock ...........................................................................................91 10.2 CPU Clock and Peripheral Function Clock................................................93 10.2.1 CPU Clock and BCLK.........................................................................93 10.2.2 ...

  • Page 10

    Interrupt Control ......................................................................................111 12.5.1 I Flag.................................................................................................113 12.5.2 IR Bit.................................................................................................113 12.5.3 ILVL2 to ILVL0 Bits and IPL .............................................................113 12.5.4 Interrupt Sequence ...........................................................................114 12.5.5 Interrupt Response Time ..................................................................115 12.5.6 Variation of IPL when Interrupt Request is Accepted .......................115 12.5.7 Saving Registers ...

  • Page 11

    Timer B....................................................................................................156 15.2.1 Timer Mode ......................................................................................159 15.2.2 Event Counter Mode.........................................................................160 15.2.3 Pulse Period and Pulse Width Measurement Mode .........................162 16. Three-Phase Motor Control Timer Function 17. Serial Interface 17.1 UARTi (i ......................................................................................176 17.1.1 Clock Synchronous Serial I/O ...

  • Page 12

    D/A Converter 20. CRC Calculation 21. Programmable I/O Ports 21.1 Port Pi Direction Register (PDi Register 13) ..............................256 21.2 Port Pi Register (Pi Register 13) ................................................256 21.3 Pull-up Control Register 0 ...

  • Page 13

    Precautions 24.1 SFR .........................................................................................................359 24.1.1 Register Settings ..............................................................................359 24.2 Reset .......................................................................................................360 24.3 Bus ..........................................................................................................361 24.4 PLL Frequency Synthesizer ....................................................................362 24.5 Power Control..........................................................................................363 24.6 Protect .....................................................................................................365 24.7 Interrupt ...................................................................................................366 24.7.1 Reading address 00000h .................................................................366 24.7.2 Setting the SP...................................................................................366 24.7.3 The ...

  • Page 14

    Program Command ..........................................................................379 24.15.7 Lock Bit Program Command ............................................................379 24.15.8 Operation speed ...............................................................................380 24.15.9 Instructions inhibited against use .....................................................380 24.15.10 Interrupts ..........................................................................................380 24.15.11 How to access ..................................................................................380 24.15.12 Writing in the user ROM area ...........................................................380 24.15.13 DMA transfer ....................................................................................381 ...

  • Page 15

    SFR Page Reference Address Register 0000h 0001h 0002h 0003h 0004h Processor Mode Register 0 0005h Processor Mode Register 1 0006h System Clock Control Register 0 0007h System Clock Control Register 1 0008h Chip Select Control Register 0009h Address Match Interrupt ...

  • Page 16

    Address Register 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h to 01AFh 01B0h 01B2h 01B3h 01B4h Flash Identification Register 01B5h Flash Memory Control Register 1 01B6h 01B7h Flash Memory Control Register 0 01B8h Address Match Interrupt Register 2 01B9h 01BAh ...

  • Page 17

    Address Register 0380h Count Start Flag 0381h Clock Prescaler Reset Fag 0382h One-Shot Start Flag 0383h Trigger Select Register 0384h Up-Down Flag 0385h 0386h Timer A0 Register 0387h 0388h Timer A1 Register 0389h 038Ah Timer A2 Register 038Bh 038Ch Timer ...

  • Page 18

    M16C/62P Group (M16C/62P, M16C/62PT) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1. Overview The M16C/62P Group (M16C/62P, M16C/62PT) of single-chip microcomputers are built using the high performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin, ...

  • Page 19

    M16C/62P Group (M16C/62P, M16C/62PT) 1.2 Performance Outline Table 1.1 to 1.3 list Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version). Table 1.1 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version) CPU Number of Basic Instructions Minimum Instruction Execution Time Operating ...

  • Page 20

    M16C/62P Group (M16C/62P, M16C/62PT) Table 1.2 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(100-pin version) Item CPU Number of Basic Instructions Minimum Instruction Execution Time Operating Mode Address Space Memory Capacity Peripheral Port Function Multifunction Timer Serial Interface A/D Converter D/A ...

  • Page 21

    M16C/62P Group (M16C/62P, M16C/62PT) Table 1.3 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(80-pin version) Item CPU Number of Basic Instructions Minimum Instruction Execution Time Operating Mode Address Space Memory Capacity Peripheral Port Function Multifunction Timer Serial Interface A/D Converter D/A ...

  • Page 22

    M16C/62P Group (M16C/62P, M16C/62PT) 1.3 Block Diagram Figure 1 M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram, Figure 1 M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram Port P0 Port P1 Internal ...

  • Page 23

    M16C/62P Group (M16C/62P, M16C/62PT) 8 Port P0 Port P2 Internal peripheral functions Timer (16-bit) Output (timer A): 5 Input (timer B): 6 Watchdog timer (15 bits) DMAC (2 channels) D/A converter (8 bits X 2 channels) NOTES : 1. ROM ...

  • Page 24

    M16C/62P Group (M16C/62P, M16C/62PT) 1.4 Product List Table 1.4 to 1.7 list the product list, Figure 1.3 shows the Type No., Memory Size, and Package, Table 1.8 lists the Product Code of Flash Memory version and ROMless version for M16C/62P, ...

  • Page 25

    M16C/62P Group (M16C/62P, M16C/62PT) Table 1.5 Product List (2) (M16C/62P) Type No. M30622MHP-XXXFP M30622MHP-XXXGP M30623MHP-XXXGP M30624MHP-XXXFP M30624MHP-XXXGP M30625MHP-XXXGP M30626MHP-XXXFP M30626MHP-XXXGP M30627MHP-XXXGP M30626MJP-XXXFP (D) 512 Kbytes M30626MJP-XXXGP (D) M30627MJP-XXXGP (D) M30622F8PFP M30622F8PGP M30623F8PGP M30620FCPFP M30620FCPGP M30621FCPGP (3) (D) 256K+4 Kbytes 20 ...

  • Page 26

    M16C/62P Group (M16C/62P, M16C/62PT) Table 1.6 Product List (3) (T version (M16C/62PT)) Type No. M3062CM6T-XXXFP (D) 48 Kbytes M3062CM6T-XXXGP (D) M3062EM6T-XXXGP (P) M3062CM8T-XXXFP (D) 64 Kbytes M3062CM8T-XXXGP (D) M3062EM8T-XXXGP (P) M3062CMAT-XXXFP (D) 96 Kbytes M3062CMAT-XXXGP (D) M3062EMAT-XXXGP (P) M3062AMCT-XXXFP (D) ...

  • Page 27

    M16C/62P Group (M16C/62P, M16C/62PT) Table 1.7 Product List (4) (V version (M16C/62PT)) Type No. M3062CM6V-XXXFP (P) 48 Kbytes M3062CM6V-XXXGP (P) M3062EM6V-XXXGP (P) M3062CM8V-XXXFP (P) 64 Kbytes M3062CM8V-XXXGP (P) M3062EM8V-XXXGP (P) M3062CMAV-XXXFP (P) 96 Kbytes M3062CMAV-XXXGP (P) M3062EMAV-XXXGP (P) M3062AMCV-XXXFP (D) ...

  • Page 28

    M16C/62P Group (M16C/62P, M16C/62PT) Type No Figure 1.3 Type No., Memory Size, and Package Rev.2.41 Jan 10, 2006 Page 11 of 390 REJ09B0185-0241 Package type: ...

  • Page 29

    M16C/62P Group (M16C/62P, M16C/62PT) Table 1.8 Product Code of Flash Memory version and ROMless version for M16C/62P Product Package Code Flash memory D3 Lead- Version included Lead-free ROM-less D3 Lead- version included D5 ...

  • Page 30

    M16C/62P Group (M16C/62P, M16C/62PT) Table 1.9 Product Code of Flash Memory version for M16C/62PT Product Code Flash T Version B memory V Version Version T Version B7 V Version T Version U V Version T Version U7 V Version M1 ...

  • Page 31

    M16C/62P Group (M16C/62P, M16C/62PT) 1.5 Pin Configuration Figures 1.6 to 1.9 show the Pin Configuration (Top View). PIN CONFIGURATION (top view) 102 101 100 P1_0/D8 103 P0_7/AN0_7/D7 104 P0_6/AN0_6/D6 105 P0_5/AN0_5/D5 106 P0_4/AN0_4/D4 107 P0_3/AN0_3/D3 108 ...

  • Page 32

    M16C/62P Group (M16C/62P, M16C/62PT) Table 1.10 Pin Characteristics for 128-Pin Package (1) Pin No. Control Pin Port 1 VREF 2 AVCC 3 P9_7 4 P9_6 5 P9_5 6 P9_4 7 P9_3 8 P9_2 9 P9_1 10 P9_0 11 P14_1 12 ...

  • Page 33

    M16C/62P Group (M16C/62P, M16C/62PT) Table 1.11 Pin Characteristics for 128-Pin Package (2) Pin No. Control Pin Port 51 P5_6 52 P5_5 53 P5_4 54 P13_3 55 P13_2 56 P13_1 57 P13_0 58 P5_3 59 P5_2 60 P5_1 61 P5_0 62 ...

  • Page 34

    M16C/62P Group (M16C/62P, M16C/62PT) Table 1.12 Pin Characteristics for 128-Pin Package (3) Pin No. Control Pin Port 101 P1_2 102 P1_1 103 P1_0 104 P0_7 105 P0_6 106 P0_5 107 P0_4 108 P0_3 109 P0_2 110 P0_1 111 P0_0 112 ...

  • Page 35

    M16C/62P Group (M16C/62P, M16C/62PT) PIN CONFIGURATION (top view P0_7/AN0_7/D7 81 P0_6/AN0_6/D6 82 P0_5/AN0_5/D5 83 P0_4/AN0_4/D4 84 P0_3/AN0_3/D3 85 P0_2/AN0_2/D2 86 P0_1/AN0_1/D1 87 P0_0/AN0_0/D0 88 P10_7/AN7/KI3 89 P10_6/AN6/KI2 90 P10_5/AN5/KI1 91 P10_4/AN4/KI0 92 P10_3/AN3 93 P10_2/AN2 94 ...

  • Page 36

    M16C/62P Group (M16C/62P, M16C/62PT) PIN CONFIGURATION (top view P1_2/D10 76 77 P1_1/D9 78 P1_0/D8 79 P0_7/AN0_7/D7 P0_6/AN0_6/ P0_5/AN0_5/D5 82 P0_4/AN0_4/D4 83 P0_3/AN0_3/D3 P0_2/AN0_2/D2 84 P0_1/AN0_1/D1 85 P0_0/AN0_0/D0 86 P10_7/AN7/KI3 87 P10_6/AN6/KI2 88 P10_5/AN5/KI1 89 90 ...

  • Page 37

    M16C/62P Group (M16C/62P, M16C/62PT) Table 1.13 Pin Characteristics for 100-Pin Package (1) Pin No. Control Pin Port P9_6 2 100 P9_5 P9_4 P9_3 5 3 P9_2 6 4 P9_1 7 5 P9_0 ...

  • Page 38

    M16C/62P Group (M16C/62P, M16C/62PT) Table 1.14 Pin Characteristics for 100-Pin Package (2) Pin No. Control Pin Port P4_3 52 50 P4_2 51 P4_1 P4_0 55 P3_7 P3_6 57 55 P3_5 ...

  • Page 39

    M16C/62P Group (M16C/62P, M16C/62PT) PIN CONFIGURATION (top view P0_6/AN0_6 61 P0_5/AN0_5 62 P0_4/AN0_4 63 P0_3/AN0_3 64 65 P0_2/AN0_2 66 P0_1/AN0_1 P0_0/AN0_0 67 P10_7/AN7/KI3 68 P10_6/AN6/KI2 69 P10_5/AN5/KI1 70 P10_4/AN4/KI0 71 P10_3/AN3 72 P10_2/AN2 73 P10_1/AN1 74 AVSS ...

  • Page 40

    M16C/62P Group (M16C/62P, M16C/62PT) Table 1.15 Pin Characteristics for 80-Pin Package (1) Pin No. Control Pin Port 1 P9_5 2 P9_4 P9_3 3 4 P9_2 5 P9_0 CNVSS 6 (BYTE) 7 XCIN P8_7 8 XCOUT P8_6 9 RESET 10 XOUT ...

  • Page 41

    M16C/62P Group (M16C/62P, M16C/62PT) Table 1.16 Pin Characteristics for 80-Pin Package (2) Pin No. Control Pin Port 51 P3_0 52 P2_7 P2_6 53 54 P2_5 55 P2_4 56 P2_3 57 P2_2 58 P2_1 59 P2_0 60 P0_7 61 P0_6 62 ...

  • Page 42

    M16C/62P Group (M16C/62P, M16C/62PT) 1.6 Pin Description Table 1.17 Pin Description (100-pin and 128-pin Version) (1) Signal Name Pin Name Power supply VCC1,VCC2 input VSS Analog power AVCC supply input AVSS Reset input RESET CNVSS CNVSS External data BYTE bus ...

  • Page 43

    M16C/62P Group (M16C/62P, M16C/62PT) Table 1.18 Pin Description (100-pin and 128-pin Version) (2) Signal Name Pin Name Main clock XIN input Main clock XOUT output Sub clock input XCIN Sub clock XCOUT output (2) BCLK output BCLK Clock output CLKOUT ...

  • Page 44

    M16C/62P Group (M16C/62P, M16C/62PT) Table 1.19 Pin Description (100-pin and 128-pin Version) (3) Signal Name Pin Name Reference VREF voltage input A/D converter AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7 ADTRG ANEX0 ANEX1 D/A converter DA0, DA1 I/O ...

  • Page 45

    M16C/62P Group (M16C/62P, M16C/62PT) Table 1.20 Pin Description (80-pin Version) (1) Signal Name Pin Name Power supply VCC1, VSS input Analog power AVCC supply input AVSS Reset input RESET CNVSS CNVSS (BYTE) Main clock XIN input Main clock XOUT output ...

  • Page 46

    M16C/62P Group (M16C/62P, M16C/62PT) Table 1.21 Pin Description (80-pin Version) (2) Signal Name Pin Name Reference VREF voltage input A/D converter AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7 ADTRG ANEX0 ANEX1 D/A converter DA0, DA1 (1) I/O port ...

  • Page 47

    M16C/62P Group (M16C/62P, M16C/62PT) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks. b31 ...

  • Page 48

    M16C/62P Group (M16C/62P, M16C/62PT) 2.2 Address Registers (A0 and A1) The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and logic/logic operations. A1 ...

  • Page 49

    M16C/62P Group (M16C/62P, M16C/62PT) 2.8.8 Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”. The U flag is cleared to “0” when a hardware interrupt ...

  • Page 50

    M16C/62P Group (M16C/62P, M16C/62PT) 3. Memory Figure 3 Memory Map of the M16C/62P group. The address space extends the 1M bytes from address 00000h to FFFFFh. The internal ROM is allocated in a lower address direction beginning with ...

  • Page 51

    M16C/62P Group (M16C/62P, M16C/62PT) 4. Special Function Register (SFR) SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.6 list the SFR information. Table 4.1 SFR Information (1) Address 0000h 0001h 0002h 0003h 0004h Processor Mode ...

  • Page 52

    M16C/62P Group (M16C/62P, M16C/62PT) Table 4.2 SFR Information (2) Address 0040h 0041h 0042h 0043h 0044h INT3 Interrupt Control Register 0045h Timer B5 Interrupt Control Register 0046h Timer B4 Interrupt Control Register, UART1 BUS Collision Detection Interrupt Control Register 0047h Timer ...

  • Page 53

    M16C/62P Group (M16C/62P, M16C/62PT) Table 4.3 SFR Information (3) Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h to 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h Flash Identification Register 01B5h Flash Memory Control Register 1 01B6h 01B7h Flash Memory Control Register ...

  • Page 54

    M16C/62P Group (M16C/62P, M16C/62PT) Table 4.4 SFR Information (4) Address 0340h Timer B3 Count Start Flag 0341h 0342h Timer A1-1 Register 0343h 0344h Timer A2-1 Register 0345h 0346h Timer A4-1 Register 0347h 0348h Three-Phase PWM Control Register 0 ...

  • Page 55

    M16C/62P Group (M16C/62P, M16C/62PT) Table 4.5 SFR Information (5) Address 0380h Count Start Flag 0381h Clock Prescaler Reset Fag 0382h One-Shot Start Flag 0383h Trigger Select Register 0384h Up-Down Flag 0385h 0386h Timer A0 Register 0387h 0388h Timer A1 Register ...

  • Page 56

    M16C/62P Group (M16C/62P, M16C/62PT) Table 4.6 SFR Information (6) Address 03C0h A/D Register 0 03C1h 03C2h A/D Register 1 03C3h 03C4h A/D Register 2 03C5h 03C6h A/D Register 3 03C7h 03C8h A/D Register 4 03C9h 03CAh A/D Register 5 03CBh ...

  • Page 57

    M16C/62P Group (M16C/62P, M16C/62PT) 5. Reset Hardware reset 1, brown-out detection reset (hardware reset 2), software reset, watchdog timer reset and oscillation stop detection reset are available to reset the microcomputer. 5.1 Hardware Reset 1 The microcomputer resets pins, the ...

  • Page 58

    M16C/62P Group (M16C/62P, M16C/62PT) VCC1, VCC2 XIN t More than d(P-R) 20 cycles are needed Microprocessor mode BYTE = H RESET BCLK Address RD WR CS0 Microprocessor mode BYTE = L Address RD WR CS0 Single chip mode Address Figure ...

  • Page 59

    M16C/62P Group (M16C/62P, M16C/62PT) Table 5.1 Pin Status When RESET Pin Level is “L” Pin Name CNVSS = VSS P0 Input port P1 Input port P2, P3, P4_0 to P4_3 Input port P4_4 Input port P4_5 to P4_7 Input port ...

  • Page 60

    M16C/62P Group (M16C/62P, M16C/62PT) 5.3 Software Reset The microcomputer resets pins, the CPU and SFR when the PM03 bit in the PM0 register is set to “1” (microcomputer reset). Then the microcomputer executes the program in an address determined by ...

  • Page 61

    M16C/62P Group (M16C/62P, M16C/62PT) 5.6 Internal Space Figure 5.3 shows CPU Register Status After Reset. Refer to 4. Special Function Register (SFR) for SFR states after reset. b19 Content of addresses FFFFEh to FFFFCh b15 IPL Figure 5.3 CPU Register ...

  • Page 62

    M16C/62P Group (M16C/62P, M16C/62PT) 6. Voltage Detection Circuit Note The M16C/62PT do not use the voltage detection circuit. However, the cold start-up/warm start-up determine function is available. The voltage detection circuit consists of the reset level detection circuit and the ...

  • Page 63

    M16C/62P Group (M16C/62P, M16C/62PT) Voltage Detection Register Symbol VCR1 Bit Symbol — (b2-b0) VC13 — (b7-b4) NOTES : 1. The VC13 bit is useful ...

  • Page 64

    M16C/62P Group (M16C/62P, M16C/62PT) Low Voltage Detection Interrupt Register Symbol D4INT Bit Symbol D40 D41 D42 D43 DF0 DF1 — (b7-b6) NOTES : 1. Write to this register after setting the PRC3 ...

  • Page 65

    M16C/62P Group (M16C/62P, M16C/62PT) Vdet4 Vdet3r VCC1 Vdet3 Vdet3s VSS RESET Internal Reset Signal VC13 bit in Indefinite VCR1 register VC26 bit in Indefinite (1) VCR2 register VC27 bit in Indefinite VCR2 register NOTES : 1. VC26 bit is invalid ...

  • Page 66

    M16C/62P Group (M16C/62P, M16C/62PT) 6.1 Low Voltage Detection Interrupt If the D40 bit in the D4INT register is set to “1” (low voltage detection interrupt enabled), the low voltage detection interrupt request is generated when the voltage applied to the ...

  • Page 67

    M16C/62P Group (M16C/62P, M16C/62PT) Low Voltage detection Circuit D4INT clock (the clock with which it VC27 operates also in wait mode) VC13 VCC1 + Noise Rejection Low Voltage VREF - detection signal (Rejection Range : 200 ns) The Low Voltage ...

  • Page 68

    M16C/62P Group (M16C/62P, M16C/62PT) 6.2 Limitations on Exiting Stop Mode The low voltage detection interrupt is immediately generated and the microcomputer exits stop mode if the CM10 bit in the CM1 register is set to “1” under the conditions below. ...

  • Page 69

    M16C/62P Group (M16C/62P, M16C/62PT) 6.4 Cold Start-up / Warm Start-up Determine Function As for the cold start-up/warm start-up determine function, the WDC5 flag in the WDC register determines either cold start-up (reset process) when power-on or warm start-up (reset process) ...

  • Page 70

    M16C/62P Group (M16C/62P, M16C/62PT) Watchdog Timer Control Register Symbol WDC Bit Symbol — (b4-b0) WDC5 — (b6) WDC7 NOTES : 1. Writing to the WDC register factors the WDC5 bit to ...

  • Page 71

    M16C/62P Group (M16C/62P, M16C/62PT) 7. Processor Mode Note The M16C/62P (80-pin version) and M16C/62PT do not use memory expansion mode, and microprocessor mode. 7.1 Types of Processor Mode Three processor modes are available to choose from: single-chip mode, memory expansion ...

  • Page 72

    M16C/62P Group (M16C/62P, M16C/62PT) 7.2 Setting Processor Modes Processor mode is set by using the CNVSS pin and the PM01 to PM00 bits in the PM0 register. Table 7.2 shows the Processor Mode After Hardware Reset. Table 7.3 shows the ...

  • Page 73

    M16C/62P Group (M16C/62P, M16C/62PT) Processor Mode Register Symbol PM0 Bit Symbol PM00 PM01 PM02 PM03 PM04 PM05 PM06 PM07 NOTES : 1. Write to this register after setting the PRC1 bit ...

  • Page 74

    M16C/62P Group (M16C/62P, M16C/62PT) Processor Mode Register Symbol PM1 Bit Symbol PM10 PM11 PM12 PM13 PM14 PM15 — (b6) PM17 NOTES : 1. Write to this register after setting the ...

  • Page 75

    M16C/62P Group (M16C/62P, M16C/62PT) Single-Chip Mode 00000h SFR 00400h Internal RAM XXXXXh Can not use YYYYYh Internal ROM FFFFFh NOTES : 1. For the mask ROM version, set the PM10 bit to “0” (08000h to 26FFFh for CS2 area). 2. ...

  • Page 76

    M16C/62P Group (M16C/62P, M16C/62PT) 8. Bus Note The M16C/62P (80-pin version) and M16C/62PT do not use bus control pins. During memory expansion or microprocessor mode, some pins serve as the bus control pins to perform data input/ output to and ...

  • Page 77

    M16C/62P Group (M16C/62P, M16C/62PT) 8.2 Bus Control The following describes the signals needed for accessing external devices and the functionality of software wait. 8.2.1 Address Bus The address bus consists of 20 lines A19. The address bus width ...

  • Page 78

    M16C/62P Group (M16C/62P, M16C/62PT) Chip Select Control Register Symbol Bit Symbol CS0 CS1 CS2 CS3 CS0W CS1W CS2W CS3W NOTES : _____ Where the RDY signal is used in the area indicated ...

  • Page 79

    M16C/62P Group (M16C/62P, M16C/62PT) Example 1 To access the external area indicated by CSj in the next cycle after accessing the external area indicated by CSi The address bus and the chip select signal both change state between these two ...

  • Page 80

    M16C/62P Group (M16C/62P, M16C/62PT) 8.2.4 Read and Write Signals When the data bus is 16 bits wide, the read and write signals can be chosen combination of RD, BHE and combination of RD, WRL ...

  • Page 81

    M16C/62P Group (M16C/62P, M16C/62PT) 8.2.6 RDY Signal This signal is provided for accessing external devices which need to be accessed at low speed. If input on the RDY pin is asserted low at the last falling edge of BCLK of ...

  • Page 82

    M16C/62P Group (M16C/62P, M16C/62PT) 8.2.7 HOLD Signal This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the input on HOLD pin is pulled low, the microcomputer is placed in ...

  • Page 83

    M16C/62P Group (M16C/62P, M16C/62PT) Table 8.6 Pin Functions for Each Processor Mode Processor Mode PM05 to PM04 bits Data Bus Width BYTE Pin P0_0 to P0_7 P1_0 to P1_7 I/O ports P2_0 A0 P2_1 to P2_7 A1 ...

  • Page 84

    M16C/62P Group (M16C/62P, M16C/62PT) 8.2.9 External Bus Status When Internal Area Accessed Table 8.7 shows the External Bus Status When Internal Area Accessed. Table 8.7 External Bus Status When Internal Area Accessed Item A0 to A19 D0 to D15 When ...

  • Page 85

    M16C/62P Group (M16C/62P, M16C/62PT) 8.2.10 Software Wait Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits in the CSR register, and the CSE register. The SFR area is unaffected ...

  • Page 86

    M16C/62P Group (M16C/62P, M16C/62PT) Table 8.8 Bit and Bus Cycle Related to Software Wait PM2 Area Bus Mode Register PM20 Bit − SFR 1 − 0 − − Internal − − RAM, ROM − External Separate Area Bus − − ...

  • Page 87

    M16C/62P Group (M16C/62P, M16C/62PT) (1) Separate Bus, No Wait Setting Write signal Read signal Data bus Address bus (2) Separate Bus, 1-Wait Setting Write signal Read signal Data bus Address bus (3) Separate Bus, 2-Wait Setting Write signal Read signal ...

  • Page 88

    M16C/62P Group (M16C/62P, M16C/62PT) (1) Separate Bus, 3-Wait Setting BCLK Write signal Read signal Data bus Address bus CS (2) Multiplexed Bus 2-Wait Setting BCLK Write signal Read signal ALE Address bus Address bus/ Data bus CS (3) ...

  • Page 89

    M16C/62P Group (M16C/62P, M16C/62PT) 9. Memory Space Expansion Function Note The M16C/62P (80-pin version) and M16C/62PT do not use the memory space expansion function. The following describes a memory space extension function. During memory expansion or microprocessor mode, the memory ...

  • Page 90

    M16C/62P Group (M16C/62P, M16C/62PT) (1) Data Bank Register Symbol DBR Bit Symbol — (b1-b0) OFS BSR0 BSR1 BSR2 — (b7-b6) NOTES : 1. Effective w hen the PM01 to PM00 bits in ...

  • Page 91

    M16C/62P Group (M16C/62P, M16C/62PT) Memory expansion mode 00000h SFR 00400h Internal RAM XXXXXh Reserved area 04000h 08000h (2) Reserved, external area 10000h 27000h Reserved area 28000h 30000h External area D0000h Reserved area YYYYYh Internal ROM FFFFFh PM13=0 Internal RAM Capacity ...

  • Page 92

    M16C/62P Group (M16C/62P, M16C/62PT) Memory expansion mode 00000h SFR 00400h Internal RAM XXXXXh 08000h (1) Reserved, external area 10000h 27000h Reserved area 28000h 30000h External area 80000h Reserved area YYYYYh Internal ROM FFFFFh PM13=1 Internal RAM Capacity Capacity Address XXXXXh ...

  • Page 93

    M16C/62P Group (M16C/62P, M16C/62PT) Memory expansion mode 00000h SFR 00400h Internal RAM XXXXXh Reserved area 04000h 08000h (3) Reserved, external area 10000h 27000h Reserved area 28000h 40000h External area C0000h D0000h Reserved area YYYYYh Internal ROM FFFFFh PM13=0 Internal RAM ...

  • Page 94

    M16C/62P Group (M16C/62P, M16C/62PT) Memory expansion mode 00000h SFR 00400h Internal RAM XXXXXh Reserved area 08000h (2) Reserved, external area 10000h 27000h Reserved area 28000h 40000h External area 80000h C0000h Reserved area YYYYYh Internal ROM FFFFFh PM13=1 Internal RAM Internal ...

  • Page 95

    M16C/62P Group (M16C/62P, M16C/62PT) Figure 9.6 shows the External Memory Connect Example in 4-Mbyte Mode. In this example, the CS pin of 4-Mbyte ROM is connected to the CS0 pin of microcomputer. The 4 Mbyte ROM address input AD21, AD20 ...

  • Page 96

    M16C/62P Group (M16C/62P, M16C/62PT) Memory expansion mode where PM13 =0 Microcomputer address ROM address OFS bit in DBR register = 0 000000h 40000h bank 0 (512 Kbytes) 040000h BFFFFh 080000h 40000h bank 1 (512 Kbytes) 0C0000h BFFFFh 100000h 40000h bank ...

  • Page 97

    M16C/62P Group (M16C/62P, M16C/62PT) Memory expansion mode where PM13 =1 ROM address Microcomputer address OFS bit in DBR register = 0 40000h 000000h bank 0 (256 Kbytes) 7FFFFh 040000h 40000h 080000h bank 1 (256 Kbytes) 7FFFFh 0C0000h 40000h 100000h bank ...

  • Page 98

    M16C/62P Group (M16C/62P, M16C/62PT) Microprocessor mode Microcomputer address ROM address OFS bit in DBR register = 0 000000h 40000h bank 0 (512 Kbytes) 040000h BFFFFh 080000h 40000h bank 1 (512 Kbytes) 0C0000h BFFFFh 100000h 40000h bank 2 (512 Kbytes) 140000h ...

  • Page 99

    M16C/62P Group (M16C/62P, M16C/62PT) 10. Clock Generation Circuit 10.1 Types of the Clock Generation Circuit 4 circuits are incorporated to generate the system clock signal : • Main clock oscillation circuit • Sub clock oscillation circuit • On-chip oscillator • ...

  • Page 100

    M16C/62P Group (M16C/62P, M16C/62PT) CM04 CM10=1(stop mode WAIT instruction R RESET Software reset NMI Interrupt request level judgment output CM02, CM04, CM05, CM06, CM07: Bits in CM0 register CM10, CM11, CM16, CM17: Bits in CM1 ...

  • Page 101

    M16C/62P Group (M16C/62P, M16C/62PT) System Clock Control Register Symbol CM0 Bit Symbol CM00 CM01 CM02 CM03 CM04 CM05 CM06 CM07 NOTES : 1. Rew rite this register after setting the PRC0 ...

  • Page 102

    M16C/62P Group (M16C/62P, M16C/62PT) System Clock Control Register Symbol CM1 Bit Symbol CM10 CM11 — (b4-b2) CM15 CM16 CM17 NOTES : 1. Rew rite this register after setting ...

  • Page 103

    M16C/62P Group (M16C/62P, M16C/62PT) Oscillation Stop Detection Register Symbol CM2 Bit Symbol CM20 CM21 CM22 CM23 — (b5-b4) — (b6) CM27 NOTES : 1. Rew rite this register after setting ...

  • Page 104

    M16C/62P Group (M16C/62P, M16C/62PT) Peripheral Clock Select Register Symbol PCLKR Bit Symbol PCLK0 PCLK1 — (b7-b2) NOTES : 1. Write to this register after setting the ...

  • Page 105

    M16C/62P Group (M16C/62P, M16C/62PT) (1, 2) PLL Control Register Symbol PLC0 Bit Symbol PLC00 PLC01 PLC02 — (b3) — (b4) — (b6-b5) PLC07 NOTES : 1. Write to ...

  • Page 106

    M16C/62P Group (M16C/62P, M16C/62PT) The following describes the clocks generated by the clock generation circuit. 10.1.1 Main Clock This clock is used as the clock source for the CPU and peripheral function clocks. This clock is used as the clock ...

  • Page 107

    M16C/62P Group (M16C/62P, M16C/62PT) 10.1.2 Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as well as the timer A and timer B count ...

  • Page 108

    M16C/62P Group (M16C/62P, M16C/62PT) 10.1.3 On-chip Oscillator Clock This clock, approximately 1MHz, is supplied by a on-chip oscillator. This clock is used as the clock source for the CPU and peripheral function clocks. In addition, if the PM22 bit in ...

  • Page 109

    M16C/62P Group (M16C/62P, M16C/62PT) Using the PLL clock as the clock source for the CPU Set the CM07 bit to “0” (main clock), the CM17 to CM16 bits to “00b” (main clock undivided), and the CM06 bit to “0” (CM16 ...

  • Page 110

    M16C/62P Group (M16C/62P, M16C/62PT) 10.2 CPU Clock and Peripheral Function Clock Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral functions. 10.2.1 CPU Clock and BCLK These are operating clocks for the ...

  • Page 111

    M16C/62P Group (M16C/62P, M16C/62PT) 10.4 Power Control Normal operating mode, wait mode and stop mode are provided as the power consumption control. All mode states, except wait mode and stop mode, are called normal operating mode in this document. 10.4.1 ...

  • Page 112

    M16C/62P Group (M16C/62P, M16C/62PT) 10.4.1.7 On-chip Oscillator Low Power Dissipation Mode The main clock is turned off after being placed in on-chip oscillator mode. The CPU clock can be selected as in the on-chip oscillator mode. The on-chip oscillator clock ...

  • Page 113

    M16C/62P Group (M16C/62P, M16C/62PT) 10.4.2 Wait Mode In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the watchdog timer. However, if the PM22 bit in the PM2 register is ...

  • Page 114

    M16C/62P Group (M16C/62P, M16C/62PT) 10.4.2.4 Exiting Wait Mode The microcomputer is moved out of wait mode by a hardware reset, NMI interrupt, low voltage detection interrupt or peripheral function interrupt. If the microcomputer moved out of exit ...

  • Page 115

    M16C/62P Group (M16C/62P, M16C/62PT) 10.4.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The ...

  • Page 116

    M16C/62P Group (M16C/62P, M16C/62PT) 10.4.3.3 Exiting Stop Mode Stop mode is exited by a hardware reset, NMI interrupt, low voltage detection interrupt or peripheral function interrupt. When the hardware reset, NMI interrupt or low voltage detection interrupt is used to ...

  • Page 117

    M16C/62P Group (M16C/62P, M16C/62PT) Main clock oscillation High-speed mode PLL operation mode PLC07=1 (6) CM11=1 CPU clock : f(PLL) CPU clock : f(XIN) CM07=0 CM07=0 CM06=0 CM06=0 CM17=0 CM17=0 PLC07=0 CM16=0 CM16=0 CM11=0 CM04=1 CM04=0 PLL operation High-speed mode mode ...

  • Page 118

    M16C/62P Group (M16C/62P, M16C/62PT) Table 10.8 Allowed Transition and Setting High-Speed Mode, Middle-Speed Mode Current High-Speed Mode, (NOTE 8) State Middle-Speed Mode (2) Low-Speed Mode Low Power Dissipation Mode PLL Operating (12) (2) Mode On-chip Oscillator (14) Mode On-chip Oscillator ...

  • Page 119

    M16C/62P Group (M16C/62P, M16C/62PT) 10.5 System Clock Protection Function The system clock protection function prohibits the CPU clock from changing clock sources when the main clock is selected the CPU clock source. This prevents the CPU clock from stopping should ...

  • Page 120

    M16C/62P Group (M16C/62P, M16C/62PT) 10.6 Oscillation Stop and Re-oscillation Detect Function The oscillation stop and re-oscillation detect function is such that main clock oscillation circuit stop and re- oscillation are detected. At oscillation stop, re-oscillation detection, reset or oscillation stop, ...

  • Page 121

    M16C/62P Group (M16C/62P, M16C/62PT) 10.6.3 How to Use Oscillation Stop and Re-oscillation Detect Function • The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer interrupt and low voltage detection interrupt. If the oscillation stop, re-oscillation ...

  • Page 122

    M16C/62P Group (M16C/62P, M16C/62PT) 11. Protection Note The M16C/62PT do not use the PRC3 bit in the PRCR register. In the event that a program runs out of control, this function protects the important registers so that they will not ...

  • Page 123

    M16C/62P Group (M16C/62P, M16C/62PT) 12. Interrupt Note The M16C/62P (80-pin version) do not use INT3 to INT5 interrupt of peripheral function. The M16C/62PT (100-pin version) do not use low voltage detection interrupt. The M16C/62PT (80-pin version) do not use low ...

  • Page 124

    M16C/62P Group (M16C/62P, M16C/62PT) 12.2 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. 12.2.1 Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. 12.2.2 Overflow Interrupt An overflow interrupt ...

  • Page 125

    M16C/62P Group (M16C/62P, M16C/62PT) 12.3 Hardware Interrupts Hardware interrupts are classified into two types − special interrupts and peripheral function interrupts. 12.3.1 Special Interrupts Special interrupts are non-maskable interrupts. 12.3.1.1 NMI Interrupt An NMI interrupt is generated when input on ...

  • Page 126

    M16C/62P Group (M16C/62P, M16C/62PT) 12.4 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the ...

  • Page 127

    M16C/62P Group (M16C/62P, M16C/62PT) 12.4.2 Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table area. Table 12.2 lists the Relocatable Vector Tables. Setting an even address in the ...

  • Page 128

    M16C/62P Group (M16C/62P, M16C/62PT) 12.5 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to nonmaskable interrupts. Use the ...

  • Page 129

    M16C/62P Group (M16C/62P, M16C/62PT) INTi ( Interrupt Control Register Symbol (4) INT3IC S4IC/INT5IC S3IC/INT4IC INT0IC to INT2IC Bit Symbol ILVL0 ILVL1 ILVL2 IR POL — (b5) — (b7-b6) NOTES ...

  • Page 130

    M16C/62P Group (M16C/62P, M16C/62PT) 12.5.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts. ...

  • Page 131

    M16C/62P Group (M16C/62P, M16C/62PT) 12.5.4 Interrupt Sequence An interrupt sequence − what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed − is described here interrupt occurs ...

  • Page 132

    M16C/62P Group (M16C/62P, M16C/62PT) 12.5.5 Interrupt Response Time Figure 12.6 shows the Interrupt Response Time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt ...

  • Page 133

    M16C/62P Group (M16C/62P, M16C/62PT) 12.5.7 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits ...

  • Page 134

    M16C/62P Group (M16C/62P, M16C/62PT) The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP time of acceptance of an interrupt request, is even or odd. If the stack pointer the PC are saved,16 ...

  • Page 135

    M16C/62P Group (M16C/62P, M16C/62PT) 12.5.8 Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the ...

  • Page 136

    M16C/62P Group (M16C/62P, M16C/62PT) 12.5.10 Interrupt Priority Level Select Circuit The interrupt priority level select circuit selects the highest priority interrupt when two or more interrupt requests are sampled at the same sampling point. Figure 12.10 shows the Interrupts Priority ...

  • Page 137

    M16C/62P Group (M16C/62P, M16C/62PT) 12.6 INT Interrupt INTi interrupt (i triggered by the edges of external inputs. The edge polarity is selected using the IFSRi bit in the IFSR register. INT4 and INT5 share the interrupt vector ...

  • Page 138

    M16C/62P Group (M16C/62P, M16C/62PT) 12.7 NMI Interrupt An NMI interrupt is generated when input on the NMI pin changes state from high to low. The NMI interrupt is a non-maskable interrupt. The input level of this NMI interrupt input pin ...

  • Page 139

    M16C/62P Group (M16C/62P, M16C/62PT) 12.9 Address Match Interrupt An address match interrupt is generated immediately before executing the instruction at the address indicated by the RMADi register (i=0 to 3). Set the start address of any instruction in the RMADi ...

  • Page 140

    M16C/62P Group (M16C/62P, M16C/62PT) Address Match Interrupt Enable Register Symbol AIER Bit Symbol AIER0 AIER1 — (b7-b2) Address Match Interrupt Enable Register Symbol ...

  • Page 141

    M16C/62P Group (M16C/62P, M16C/62PT) 13. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a ...

  • Page 142

    M16C/62P Group (M16C/62P, M16C/62PT) Watchdog Timer Control Register Symbol WDC Bit Symbol — (b4-b0) WDC5 — (b6) WDC7 NOTES : 1. Writing to the WDC register factors the WDC5 bit to ...

  • Page 143

    M16C/62P Group (M16C/62P, M16C/62PT) 14. DMAC The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit) data ...

  • Page 144

    M16C/62P Group (M16C/62P, M16C/62PT) Table 14.1 DMAC Specifications Item No. of Channels Transfer Memory Space Maximum No. of Bytes Transferred (1, 2) DMA Request Factors Channel Priority Transfer Unit Transfer Address Direction Transfer Mode Single Transfer Repeat Transfer DMA Interrupt ...

  • Page 145

    M16C/62P Group (M16C/62P, M16C/62PT) DMA0 Request Factor Select Register Symbol DM0SL Bit Symbol DSEL0 DSEL1 DSEL2 DSEL3 — (b5-b4) DMS DSR NOTES : 1. The factors of DMA0 requests can be selected ...

  • Page 146

    M16C/62P Group (M16C/62P, M16C/62PT) DMA1 Request Factor Select Register Symbol DM1SL Bit Symbol DSEL0 DSEL1 DSEL2 DSEL3 — (b5-b4) DMS DSR NOTES : 1. The factors of DMA1 requests can be selected ...

  • Page 147

    M16C/62P Group (M16C/62P, M16C/62PT) DMAi Control Register (i=0, Symbol DM0CON DM1CON Bit Symbol DMBIT DMASL DMAS DMAE DSD DAD — (b7-b6) NOTES : 1. The DMAS bit can be set to “0” ...

  • Page 148

    M16C/62P Group (M16C/62P, M16C/62PT) DMAi Source Pointer ( (b23) (b19) (b16) (b15 Set the source address of transfer Nothing is assigned. When w rite, set “0”. When read, their contents are “0”. NOTES ...

  • Page 149

    M16C/62P Group (M16C/62P, M16C/62PT) 14.1 Transfer Cycles The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read and write bus cycles is affected by the ...

  • Page 150

    M16C/62P Group (M16C/62P, M16C/62PT) (1) When the transfer unit bits and the source of transfer is an even address BCLK Address CPU use bus RD signal WR signal Data bus CPU use (2) When the transfer ...

  • Page 151

    M16C/62P Group (M16C/62P, M16C/62PT) 14.2 DMA Transfer Cycles Any combination of even or odd transfer read and write addresses is possible. Table 14.2 lists the DMA Transfer Cycles. Table 14.3 lists the Coefficient j, k. The number of DMAC transfer ...

  • Page 152

    M16C/62P Group (M16C/62P, M16C/62PT) 14.3 DMA Enable When a data transfer starts after setting the DMAE bit in the DMiCON register ( “1” (enabled), the DMAC operates as follows: (1) Reload the forward address pointer with ...

  • Page 153

    M16C/62P Group (M16C/62P, M16C/62PT) 14.5 Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected active in the same sampling period (one period from a falling ...

  • Page 154

    M16C/62P Group (M16C/62P, M16C/62PT) 15. Timers Note The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include TA1IN, TA1OUT, TA2IN, TA2OUT and TB pins. Do not use the function which needs these pins. Eleven 16-bit timers, each capable of ...

  • Page 155

    M16C/62P Group (M16C/62P, M16C/62PT) 1/2 · Main clock f1 · PLL clock · On-chip oscillator clock 1 f32 fC32 TCK1 to TCK0 TB0IN TCK1 to TCK0 TB1IN TCK1 ...

  • Page 156

    M16C/62P Group (M16C/62P, M16C/62PT) 15.1 Timer A Note The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include TA1IN and TA1OUT pins of Timer A1, and TA2IN and TA2OUT pins of Timer A2 . [Precautions when using Timer A1 ...

  • Page 157

    M16C/62P Group (M16C/62P, M16C/62PT) Timer Ai Mode Register (i Symbol TA0MR to TA4MR Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 (1) Timer Ai Register ( ...

  • Page 158

    M16C/62P Group (M16C/62P, M16C/62PT) Count Start Flag Symbol TABSR Bit Symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Up/Down Flag ( Symbol UDF ...

  • Page 159

    M16C/62P Group (M16C/62P, M16C/62PT) One-Shot Start Flag Symbol ONSF Bit Symbol TA0OS TA1OS TA2OS TA3OS TA4OS TAZIE TA0TGL TA0TGH NOTES : 1. Make sure the PD7_1 bit in the PD7 register is ...

  • Page 160

    M16C/62P Group (M16C/62P, M16C/62PT) Clock Prescaler Reset Flag Symbol CPSRF Bit Symbol — (b6-b0) CPSR Figure 15.7 CPSRF Register Rev.2.41 Jan 10, 2006 Page 143 of 390 REJ09B0185-0241 Address 0381h Bit Name ...

  • Page 161

    M16C/62P Group (M16C/62P, M16C/62PT) 15.1.1 Timer Mode In timer mode, the timer counts a count source generated internally (see Table 15.1). Figure 15.8 shows TAiMR Register in Timer Mode. Table 15.1 Specifications in Timer Mode Item Count source f1, f2, ...

  • Page 162

    M16C/62P Group (M16C/62P, M16C/62PT) Timer Ai Mode Register (i TA0MR to TA4MR Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 NOTES : 1. TA0OUT pin ...

  • Page 163

    M16C/62P Group (M16C/62P, M16C/62PT) 15.1.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timer A2, A3 and A4 can count two-phase external signals. Table 15.2 lists ...

  • Page 164

    M16C/62P Group (M16C/62P, M16C/62PT) Timer Ai Mode Register (i (when not using two-phase pulse signal processing Symbol TA0MR to TA4MR Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 ...

  • Page 165

    M16C/62P Group (M16C/62P, M16C/62PT) Table 15.3 Specifications in Event Counter Mode (when processing two-phase pulse signal with Timer A2, A3 and A4) Item Count Source • Two-phase pulse signals input to TAiIN or TAiOUT pins (i Count Operation ...

  • Page 166

    M16C/62P Group (M16C/62P, M16C/62PT) Timer A2 Mode Register (i (when using two-phase pulse signal processing Symbol TA2MR to TA4MR Bit Symbol TMOD0 TMOD1 MR0 ...

  • Page 167

    M16C/62P Group (M16C/62P, M16C/62PT) 15.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two-phase pulse signal processing. This function can only be used in Timer A3 ...

  • Page 168

    M16C/62P Group (M16C/62P, M16C/62PT) 15.1.3 One-shot Timer Mode In one-shot timer mode, the timer is activated only once by one trigger (see Table 15.4). When the trigger occurs, the timer starts up and continues operating for a given period. Figure ...

  • Page 169

    M16C/62P Group (M16C/62P, M16C/62PT) Timer Ai Mode Register (i Symbol TA0MR to TA4MR Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 NOTES : 1. TA0OUT ...

  • Page 170

    M16C/62P Group (M16C/62P, M16C/62PT) 15.1.4 Pulse Width Modulation (PWM) Mode In PWM mode, the timer outputs pulses of a given width in succession (see Table 15.5). The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. ...

  • Page 171

    M16C/62P Group (M16C/62P, M16C/62PT) Timer Ai Mode Register ( Symbol TA0MR to TA4MR Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 NOTES : 1. TA0OUT ...

  • Page 172

    M16C/62P Group (M16C/62P, M16C/62PT) Count source “H” Input signal to TAiIN pin “L” “H” PWM pulse output from TAiOUT pin “L” “1” IR bit in TAiIC register “0” Frequency of count source (f1, f2, f8, f32, fC32) i ...

  • Page 173

    M16C/62P Group (M16C/62P, M16C/62PT) 15.2 Timer B Note The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include TB1IN pin of Timer B1. [Precautions when using TimerB2] • Event Counter Mode • Pulse Period/Pulse Width Measurement Mode Figure 15.16 ...

  • Page 174

    M16C/62P Group (M16C/62P, M16C/62PT) Timer Bi Mode Register (i Symbol TB0MR to TB2MR TB3MR to TB5MR Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 NOTES : 1. Timer ...

  • Page 175

    M16C/62P Group (M16C/62P, M16C/62PT) Count Start Flag Symbol TABSR Bit Symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Timer B3, B4, B5 Count Start Flag ...

  • Page 176

    M16C/62P Group (M16C/62P, M16C/62PT) 15.2.1 Timer Mode In timer mode, the timer counts a count source generated internally (see Table 15.6). Figure 15.19 shows TBiMR Register in Timer Mode. Table 15.6 Specifications in Timer Mode Item Count Source f1, f2, ...

  • Page 177

    M16C/62P Group (M16C/62P, M16C/62PT) 15.2.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers (see Table 15.7). Figure 15.20 shows TBiMR Register in Event Counter Mode. Table ...

  • Page 178

    M16C/62P Group (M16C/62P, M16C/62PT) . Timer Bi Mode Register (i Symbol TB0MR to TB2MR TB3MR to TB5MR Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 NOTES ...

  • Page 179

    M16C/62P Group (M16C/62P, M16C/62PT) 15.2.3 Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal (see Table 15.8). Figure 15.21 shows TBiMR Register ...

  • Page 180

    M16C/62P Group (M16C/62P, M16C/62PT) Timer Bi Mode Register (i Symbol TB0MR to TB2MR TB3MR to TB5MR Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 NOTES : ...

  • Page 181

    M16C/62P Group (M16C/62P, M16C/62PT) Count source “H” Measurement pulse “L” Reload register counter transfer timing Timing at which counter reaches “0000h” “1” TBiS bit “0” “1” IR bit in TBiIC register “0” “1” MR3 bit in TBiMR register “0” The ...

  • Page 182

    M16C/62P Group (M16C/62P, M16C/62PT) 16. Three-Phase Motor Control Timer Function Note The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not use this function. Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table ...

  • Page 183

    M16C/62P Group (M16C/62P, M16C/62PT) INV00 to INV07: Bits in INVC0 Register INV10 to INV15: Bits in INVC1 Register DUi, DUBi: Bits in IDBi Register (i=0,1) TA1S to TA4S: Bits in TABSR Register PWCOM: Bits in TB2SC Register INV00 Reload Control ...

  • Page 184

    M16C/62P Group (M16C/62P, M16C/62PT) Three-Phase Control Register Symbol INVC0 Bit Symbol INV00 INV01 INV02 INV03 INV04 INV05 INV06 INV07 NOTES : 1. Set the INVC0 register af ter the PRC1 bit ...

  • Page 185

    M16C/62P Group (M16C/62P, M16C/62PT) Three-Phase Control Register Symbol INVC1 Bit Symbol INV10 INV11 INV12 INV13 INV14 INV15 INV16 — (b7) NOTES : 1. Rew rite the INVC1 register after the ...

  • Page 186

    M16C/62P Group (M16C/62P, M16C/62PT) Timer B2 Interrupt Generation Frequency Set Counter b7 b0 Symbol ICTB2 When the INV01 bit is set to “0” (the ICTB2 counter increments w henever Timer B2 underflow s) and the setting value ...

  • Page 187

    M16C/62P Group (M16C/62P, M16C/62PT) Timer B2 Special Mode Register Symbol TB2SC Bit Symbol PWCOM IVPCR1 — (b7-b2) NOTES : 1. Write to this register after setting the PRC1 bit in the PRCR ...

  • Page 188

    M16C/62P Group (M16C/62P, M16C/62PT) (1, 2) Dead Time Timer b7 b0 Symbol DTT If setting value the timer stops w hen counting n times a count source selected by the INV12 after start trigger occurs. Positive or ...

  • Page 189

    M16C/62P Group (M16C/62P, M16C/62PT) Count Start Flag Symbol TABSR Bit Symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S Figure 16.7 TABSR Register Rev.2.41 Jan 10, 2006 Page 172 of 390 REJ09B0185-0241 ...

  • Page 190

    M16C/62P Group (M16C/62P, M16C/62PT) Timer Ai Mode Register (i= Symbol TA1MR, TA2MR TA4MR Bit Symbol TMOD0 TMOD1 MR0 MR1 MR2 MR3 TCK0 TCK1 NOTES ...

  • Page 191

    M16C/62P Group (M16C/62P, M16C/62PT) The three-phase motor control timer function is enabled by setting the INV02 bit in the INVC0 register to “1”. When this function is on, timer B2 is used to control the carrier wave, and timers A4, ...

  • Page 192

    M16C/62P Group (M16C/62P, M16C/62PT) Sawtooth Waveform as a Carrier Wave Sawtooth Wave Signal Wave Timer B2 Timer A4 Start (1) Trigger Signal Timer A4 One-Shot (1) Pulse U-Phase Output (1) Signal U-Phase Output (1) Signal U-Phase INV14 = 0 (“L” ...

  • Page 193

    M16C/62P Group (M16C/62P, M16C/62PT) 17. Serial Interface Note The M16C/62P (80-pin version) and M16C/62PT (80-pin version) do not include CLK2, CTS2/RTS2 and SIN pins. Do not use the function which needs these pins. Serial interface is configured with 5 channels: ...

  • Page 194

    M16C/62P Group (M16C/62P, M16C/62PT) Main clock, PLL clock, or on-chip oscillator clock (UART0) RXD polarity RXD0 reversing circuit Clock source selection CLK1 to CLK0 CKDIR 00h Internal f1SIO or f2SIO 01h 0 f8SIO 10h f32SIO 1 External CKPOL Clock synchronous ...

  • Page 195

    M16C/62P Group (M16C/62P, M16C/62PT) Main clock, PLL clock, or on-chip oscillator clock (UART1) RXD polarity reversing RXD1 circuit Clock source selection CLK1 to CLK0 CKDIR 00 f1SIO or f2SIO Internal 01 0 f8SIO 10 f32SIO 1 External Clock synchronous type ...

  • Page 196

    M16C/62P Group (M16C/62P, M16C/62PT) Main clock, PLL clock, or on-chip oscillator clock (UART2) RXD polarity reversing RXD2 circuit Clock source selection CLK1 to CLK0 CKDIR 00 Internal f1SIO or f2SIO 01 0 f8SIO 10 f32SIO 1 External Clock synchronous type ...

  • Page 197

    M16C/62P Group (M16C/62P, M16C/62PT) IOPOL No reverse RXDi 0 RXD data reverse circuit 1 Reverse PRYE STPS 1SP PAR 1 1 PAR enabled 2SP PRYE STPS PAR 2SP enabled PAR ...

  • Page 198

    M16C/62P Group (M16C/62P, M16C/62PT) UARTi Transmit Buffer Register (i (b15) (b8 Transmit data Nothing is assigned. When w rite, set to “0”. When read, their contents are indeterminate. NOTES : 1. Use MOV instruction to ...

  • Page 199

    M16C/62P Group (M16C/62P, M16C/62PT) UARTi Bit Rate Generator Register (i Assuming that set value = n, UiBRG divides the count source NOTES : 1. Write to this register w hile serial interface ...

  • Page 200

    M16C/62P Group (M16C/62P, M16C/62PT) UARTi Transmit/Receive Mode Register (i Symbol U0MR to U2MR Bit Symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE IOPOL NOTES : 1. Set the corresponding port ...