C8051F021-GQR Silicon Laboratories Inc, C8051F021-GQR Datasheet - Page 150

• Manufacturer Part Number: C8051F021-GQR
• Description: IC 8051 MCU 64K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F02xr

Specifications of C8051F021-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: 336-1200 - DEV KIT FOR F020/F021/F022/F023
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

C8051F020/1/2/3
16.5. Memory Mode Selection
The external data memory space can be configured in one of four modes, shown in Figure 16.5, based on the EMIF
Mode bits in the EMI0CF register (Figure 16.2). These modes are summarized below. More information about the
different modes can be found in
16.5.1. Internal XRAM Only
When EMI0CF.[3:2] are set to ‘00’, all MOVX instructions will target the internal XRAM space on the device. Mem-
ory accesses to addresses beyond the populated space will wrap on 4k boundaries. As an example, the addresses
0x1000 and 0x2000 both evaluate to address 0x0000 in on-chip XRAM space.
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•
16.5.2. Split Mode without Bank Select
When EMI0CF.[3:2] are set to ‘01’, the XRAM memory map is split into two areas, on-chip space and off-chip space.
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150
EMI0CF[3:2] = 00
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
On-Chip XRAM
8-bit MOVX operations use the contents of EMI0CN to determine the high-byte of the effective address and R0
or R1 to determine the low-byte of the effective address.
16-bit MOVX operations use the contents of the 16-bit DPTR to determine the effective address.
Effective addresses below the 4k boundary will access on-chip XRAM space.
Effective addresses beyond the 4k boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-chip or off-
chip. The lower 8-bits of the Address Bus A[7:0] are driven as defined by R0 or R1. However, in the “No Bank
Select” mode, an 8-bit MOVX operation will not drive the upper 8-bits A[15:8] of the Address Bus during an
off-chip access. This allows the user to manipulate the upper address bits at will by setting the Port state directly.
This behavior is in contrast with “Split Mode with Bank Select” described below.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip or off-
chip, and unlike 8-bit MOVX operations, the full 16-bits of the Address Bus A[15:0] are driven during the off-
chip transaction.
0xFFFF
0x0000
EMI0CF[3:2] = 01
(No Bank Select)
On-Chip XRAM
Section “ .” on page
Off-Chip
Memory
Figure 16.5. EMIF Operating Modes
0xFFFF
0x0000
152.
Rev. 1.4
EMI0CF[3:2] = 10
On-Chip XRAM
(Bank Select)
Off-Chip
Memory
0xFFFF
0x0000
EMI0CF[3:2] = 11
Off-Chip
Memory
0xFFFF
0x0000