C8051F021-GQR Silicon Laboratories Inc, C8051F021-GQR Datasheet - Page 191

• Manufacturer Part Number: C8051F021-GQR
• Description: IC 8051 MCU 64K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F02xr

Specifications of C8051F021-GQR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: 336-1200 - DEV KIT FOR F020/F021/F022/F023
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
BUSY
Bit7
R
BUSY: Busy Status Flag.
0: SMBus0 is free
1: SMBus0 is busy
ENSMB: SMBus Enable.
This bit enables/disables the SMBus serial interface.
0: SMBus0 disabled.
1: SMBus0 enabled.
STA: SMBus Start Flag.
0: No START condition is transmitted.
1: When operating as a master, a START condition is transmitted if the bus is free. (If the bus is not
free, the START is transmitted after a STOP is received.) If STA is set after one or more bytes have
been transmitted or received and before a STOP is received, a repeated START condition is transmit-
ted. To ensure proper operation, the STO bit should be explicitly cleared to ‘0’ before setting the STA
bit to ‘1’.
STO: SMBus Stop Flag.
0: No STOP condition is transmitted.
1: Setting STO to logic 1 causes a STOP condition to be transmitted. When a STOP condition is
received, hardware clears STO to logic 0. If both STA and STO are set, a STOP condition is transmit-
ted followed by a START condition. In slave mode, setting the STO flag causes SMBus to behave as
if a STOP condition was received.
SI: SMBus Serial Interrupt Flag.
This bit is set by hardware when one of 27 possible SMBus0 states is entered. (Status code 0xF8 does
not cause SI to be set.) When the SI interrupt is enabled, setting this bit causes the CPU to vector to
the SMBus interrupt service routine. This bit is not automatically cleared by hardware and must be
cleared by software.
AA: SMBus Assert Acknowledge Flag.
This bit defines the type of acknowledge returned during the acknowledge cycle on the SCL line.
0: A "not acknowledge" (high level on SDA) is returned during the acknowledge cycle.
1: An "acknowledge" (low level on SDA) is returned during the acknowledge cycle.
FTE: SMBus Free Timer Enable Bit
0: No timeout when SCL is high
1: Timeout when SCL high time exceeds limit specified by the SMB0CR value.
TOE: SMBus Timeout Enable Bit
0: No timeout when SCL is low.
ENSMB
R/W
Bit6
Figure 18.8. SMB0CN: SMBus0 Control Register
STA
R/W
Bit5
STO
R/W
Bit4
R/W
Bit3
SI
Rev. 1.4
R/W
AA
Bit2
C8051F020/1/2/3
FTE
R/W
Bit1
(bit addressable)
TOE
R/W
Bit0
SFR Address:
00000000
Reset Value
0xC0
191