C8051F020-GQR

Manufacturer Part NumberC8051F020-GQR
DescriptionIC 8051 MCU 64K FLASH 100TQFP
ManufacturerSilicon Laboratories Inc
SeriesC8051F02x
C8051F020-GQR datasheets
 

Specifications of C8051F020-GQR

Core Processor8051Core Size8-Bit
Speed25MHzConnectivityEBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
PeripheralsBrown-out Detect/Reset, POR, PWM, Temp Sensor, WDTNumber Of I /o64
Program Memory Size64KB (64K x 8)Program Memory TypeFLASH
Ram Size4.25K x 8Voltage - Supply (vcc/vdd)2.7 V ~ 3.6 V
Data ConvertersA/D 8x8b, 8x12b; D/A 2x12bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case100-TQFP, 100-VQFP
For Use With336-1200 - DEV KIT FOR F020/F021/F022/F023Lead Free Status / RoHS StatusLead free / RoHS Compliant
Eeprom Size-  
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25 MIPS, 64 kB Flash, 12-Bit ADC, 100-Pin Mixed-Signal MCU
Analog Peripherals
12-Bit ADC
-
±1 LSB INL; no missing codes
-
Programmable throughput up to 100 ksps
-
8 external inputs; programmable as single-ended or differential
-
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
-
Data-dependent windowed interrupt generator
-
Built-in temperature sensor (±3 °C)
8-Bit ADC
-
±1 LSB INL; no missing codes
-
Programmable throughput up to 500 ksps
-
8 external inputs
-
Programmable amplifier gain: 4, 2, 1, 0.5
Two 12-Bit DACs
-
Can synchronize outputs to timers for jitter-free waveform generation
Two Comparators
Internal Voltage Reference
V
Monitor/Brown-out Detector
DD
On-Chip JTAG Debug & Boundary Scan
-
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
-
Provides breakpoints, single stepping, watchpoints, stack monitor
-
Inspect/modify memory and registers
-
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
-
IEEE1149.1 compliant boundary scan
VDD
VDD
VDD
Digital Power
DGND
DGND
DGND
AV+
AV+
Analog Power
AGND
AGND
TCK
Boundary Scan
JTAG
TMS
Logic
TDI
Debug HW
TDO
Reset
RST
VDD
WDT
MONEN
Monitor
External
XTAL1
Oscillator
XTAL2
Circuit
System
Clock
Internal
Oscillator
VREF
VREF
VREFD
DAC1
DAC1
(12-Bit)
DAC0
DAC0
(12-Bit)
VREF0
AIN0.0
AIN0.1
ADC
AIN0.2
A
AIN0.3
M
100 ksps
Prog
AIN0.4
U
Gain
(12-Bit)
AIN0.5
X
AIN0.6
AIN0.7
TEMP
SENSOR
CP0+
CP0
CP0-
CP1+
CP1
CP1-
Precision Mixed Signal
High-Speed 8051 µC Core
-
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
-
Up to 25 MIPS throughput with 25 MHz system clock
-
22 vectored interrupt sources
Memory
-
4352 bytes data RAM
-
64 kB Flash; in-system programmable in 512-byte sectors (512 bytes
are reserved)
-
External parallel data memory interface
Digital Peripherals
-
64 port I/O; all are 5 V tolerant
-
Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial
ports available concurrently
-
Programmable 16-bit counter/timer array with 5 capture/compare mod-
ules
-
5 general-purpose 16-bit counter/timers
-
Dedicated watchdog timer; bidirectional reset
-
Real-time clock mode using Timer 3 or PCA
Clock Sources
-
Internal programmable oscillator: 2–16 MHz
-
External oscillator: Crystal, RC, C, or Clock
-
Can switch between clock sources on-the-fly
Supply Voltage: 2.7 to 3.6 V
-
Typical operating current: 10 mA at 25 MHz
-
Multiple power saving sleep and shutdown modes
100-Pin TQFP
Temperature Range: –40 to +85 °C
8
UART0
UART1
0
SMBus
SPI Bus
5
PCA
1
Timers 0,
SFR Bus
1, 2, 4
Timer 3/
RTC
64 kB
C
P0, P1,
FLASH
P2, P3
o
Latches
256 Byte
Crossbar
RAM
r
Config.
4 kB
e
RAM
External Data Memory Bus
Copyright © 2007 by Silicon Laboratories
C8051F020
P0.0
P0
Drv
P0.7
C
R
P1
P1.0/AIN1.0
O
Drv
P1.7/AIN1.7
S
S
B
P2.0
P2
Drv
A
P2.7
R
P3.0
P3
Drv
P3.7
VREF1
A
ADC
8:1
M
500 ksps
Prog
Gain
U
(8-Bit)
X
P4.0
C
C
P4 Latch
Bus Control
P4
P4.4
T
DRV
P4.5
L
P4.6
P4.7
P5.0
P5 Latch
P5
A
DRV
P5.7
Address Bus
d
d
P6.0
P6 Latch
P6
r
DRV
P6.7
D
P7.0
P7 Latch
P7
Data Bus
a
DRV
P7.7
t
a
11.02.2007

C8051F020-GQR Summary of contents

  • Page 1

    ... SMBus SPI Bus 5 PCA 1 Timers 0, SFR Bus Timer 3/ RTC P0, P1, FLASH P2 Latches 256 Byte Crossbar RAM r Config RAM External Data Memory Bus Copyright © 2007 by Silicon Laboratories C8051F020 P0.0 P0 Drv P0 P1.0/AIN1.0 O Drv P1.7/AIN1 P2.0 P2 Drv A P2.7 R P3.0 P3 Drv P3.7 VREF1 A ADC ...

  • Page 2

    ... Enabled Oscillator not running; V Monitor DD Disabled –3 mA, Port I/O push-pull V – Guaranteed Monotonic 66 0 Guaranteed Monotonic (each Comparator 2 (CP+) – (CP 100 mV –0.25 –5 –10 C8051F020DK Development Kit MIN NOM MAX (mm) (mm) (mm 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 b 0.17 0.22 0. 16.00 - ...