C8051F020-GQR Silicon Laboratories Inc, C8051F020-GQR Datasheet

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C8051F020-GQR

Manufacturer Part Number
C8051F020-GQR
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Datasheets

Specifications of C8051F020-GQR

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Analog Peripherals
12-Bit ADC
-
-
-
-
-
-
8-Bit ADC
-
-
-
-
Two 12-Bit DACs
-
Two Comparators
Internal Voltage Reference
V
On-Chip JTAG Debug & Boundary Scan
-
-
-
-
-
Precision Mixed Signal
DD
MONEN
VREFD
XTAL1
XTAL2
VREF0
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
±1 LSB INL; no missing codes
Programmable throughput up to 100 ksps
8 external inputs; programmable as single-ended or differential
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
Data-dependent windowed interrupt generator
Built-in temperature sensor (±3 °C)
±1 LSB INL; no missing codes
Programmable throughput up to 500 ksps
8 external inputs
Programmable amplifier gain: 4, 2, 1, 0.5
Can synchronize outputs to timers for jitter-free waveform generation
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
Provides breakpoints, single stepping, watchpoints, stack monitor
Inspect/modify memory and registers
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
IEEE1149.1 compliant boundary scan
DGND
DGND
DGND
AGND
AGND
DAC1
DAC0
VREF
CP0+
CP1+
CP0-
CP1-
VDD
VDD
VDD
TCK
TMS
TDO
RST
Monitor/Brown-out Detector
AV+
AV+
TDI
CP0
A
M
U
X
Analog Power
Digital Power
Oscillator
Oscillator
External
Monitor
Internal
Circuit
VDD
CP1
JTAG
Logic
(12-Bit)
(12-Bit)
VREF
DAC1
DAC0
SENSOR
TEMP
Prog
Gain
Boundary Scan
WDT
Debug HW
System
Clock
25 MIPS, 64 kB Flash, 12-Bit ADC, 100-Pin Mixed-Signal MCU
100 ksps
(12-Bit)
ADC
Reset
Copyright © 2007 by Silicon Laboratories
8
0
5
1
C
o
r
e
External Data Memory Bus
256 Byte
SFR Bus
FLASH
64 kB
RAM
4 kB
RAM
High-Speed 8051 µC Core
-
-
-
Memory
-
-
-
Digital Peripherals
-
-
-
-
-
-
Clock Sources
-
-
-
Supply Voltage: 2.7 to 3.6 V
-
-
100-Pin TQFP
Temperature Range: –40 to +85 °C
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
Up to 25 MIPS throughput with 25 MHz system clock
22 vectored interrupt sources
4352 bytes data RAM
64 kB Flash; in-system programmable in 512-byte sectors (512 bytes
are reserved)
External parallel data memory interface
64 port I/O; all are 5 V tolerant
Hardware SMBus™ (I2C™ compatible), SPI™, and two UART serial
ports available concurrently
Programmable 16-bit counter/timer array with 5 capture/compare mod-
ules
5 general-purpose 16-bit counter/timers
Dedicated watchdog timer; bidirectional reset
Real-time clock mode using Timer 3 or PCA
Internal programmable oscillator: 2–16 MHz
External oscillator: Crystal, RC, C, or Clock
Can switch between clock sources on-the-fly
Typical operating current: 10 mA at 25 MHz
Multiple power saving sleep and shutdown modes
Timers 0,
Crossbar
Timer 3/
SPI Bus
Latches
UART0
UART1
P0, P1,
SMBus
Config.
1, 2, 4
P2, P3
PCA
RTC
Address Bus
Bus Control
Data Bus
500 ksps
(8-Bit)
ADC
C
D
T
L
A
d
d
a
a
r
t
C
R
O
S
S
B
A
R
C
P4 Latch
P5 Latch
P6 Latch
P7 Latch
C8051F020
Prog
Gain
Drv
Drv
Drv
Drv
P0
P1
P2
P3
A
M
U
X
8:1
DRV
DRV
DRV
DRV
P4
P5
P6
P7
11.02.2007
P0.0
P0.7
P1.7/AIN1.7
P2.0
P2.7
P3.0
P3.7
P1.0/AIN1.0
VREF1
P5.0
P7.0
P7.7
P4.0
P4.4
P4.5
P4.6
P4.7
P5.7
P6.0
P6.7

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C8051F020-GQR Summary of contents

Page 1

... SMBus SPI Bus 5 PCA 1 Timers 0, SFR Bus Timer 3/ RTC P0, P1, FLASH P2 Latches 256 Byte Crossbar RAM r Config RAM External Data Memory Bus Copyright © 2007 by Silicon Laboratories C8051F020 P0.0 P0 Drv P0 P1.0/AIN1.0 O Drv P1.7/AIN1 P2.0 P2 Drv A P2.7 R P3.0 P3 Drv P3.7 VREF1 A ADC ...

Page 2

... Enabled Oscillator not running; V Monitor DD Disabled –3 mA, Port I/O push-pull V – Guaranteed Monotonic 66 0 Guaranteed Monotonic (each Comparator 2 (CP+) – (CP 100 mV –0.25 –5 –10 C8051F020DK Development Kit MIN NOM MAX (mm) (mm) (mm 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 b 0.17 0.22 0. 16.00 - ...

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