HD64F2612FA20 Renesas Electronics America, HD64F2612FA20 Datasheet
HD64F2612FA20
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HD64F2612FA20 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/2612 Group, 16 H8S/2612 F-ZTAT Hardware Manual ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Main Revisions for This Edition 5. Contents 6. Overview 7. Description of Functional ...
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The H8S/2612 Group are single-chip microcomputers made up of the high-speed H8S/2600 CPU as its core, and the peripheral functions required to configure a system. The H8S/2600 CPU has an instruction set that is compatible with the H8/300 and H8/300H ...
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In order to understand the details of a register when its name is known Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bits, ...
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Main Revisions for This Edition Item Page 8.5.7 Number of DTC 122 Execution States 14.7.6 Data 370 Transmission (Except for Block Transfer Mode) Figure 14.26 Retransfer Operation in SCI Transmit Mode 14.7.7 Serial Data 371 Reception (Except for Block Transfer ...
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Item Page 18.8.3 Interrupt 473 Handling when Programming/Erasing Flash Memory Figure 18.10 Erase/Erase-Verify Flowchart All trademarks and registered trademarks are the property of their respective owners. Rev. 7.00 Sep. 11, 2009 Page viii of xxxiv REJ09B0211-0700 Revision (See Manual for ...
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Section 1 Overview................................................................................................1 1.1 Overview................................................................................................................................ 1 1.2 Internal Block Diagram.......................................................................................................... 3 1.3 Pin Arrangement .................................................................................................................... 5 1.4 Pin Functions ......................................................................................................................... 7 1.5 Differences between H8S/2612, H8S/2611, H8S/2614, and H8S/2616............................... 12 Section 2 CPU......................................................................................................13 2.1 Features ................................................................................................................................ 13 2.1.1 Differences between ...
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Processing States.................................................................................................................. 48 2.9 Usage Notes ......................................................................................................................... 49 2.9.1 Usage Notes on Bit Manipulation Instructions ....................................................... 49 Section 3 MCU Operating Modes .......................................................................51 3.1 Operating Mode Selection ................................................................................................... 51 3.2 Register Descriptions ........................................................................................................... 51 3.2.1 Mode Control Register (MDCR) ...
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Interrupt Control Mode 2 ........................................................................................ 81 5.6.3 Interrupt Exception Handling Sequence ................................................................. 83 5.6.4 Interrupt Response Times ....................................................................................... 85 5.6.5 DTC Activation by Interrupt................................................................................... 86 5.7 Usage Notes ......................................................................................................................... 86 5.7.1 Contention between Interrupt Generation and Disabling........................................ 86 5.7.2 ...
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Bus Arbitration................................................................................................................... 101 7.2.1 Order of Priority of the Bus Masters..................................................................... 101 7.2.2 Bus Transfer Timing ............................................................................................. 101 Section 8 Data Transfer Controller (DTC) ........................................................103 8.1 Features .............................................................................................................................. 103 8.2 Register Configuration....................................................................................................... 105 8.2.1 DTC Mode Register A (MRA) ...
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Port 1 Register (PORT1)....................................................................................... 131 9.1.4 Pin Functions ........................................................................................................ 132 9.2 Port 4.................................................................................................................................. 135 9.2.1 Port 4 Register (PORT4)....................................................................................... 135 9.3 Port 9.................................................................................................................................. 136 9.3.1 Port 9 Register (PORT9)....................................................................................... 136 9.4 Port A................................................................................................................................. 137 9.4.1 Port A Data Direction ...
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Register Descriptions ......................................................................................................... 164 10.3.1 Timer Control Register (TCR) .............................................................................. 166 10.3.2 Timer Mode Register (TMDR) ............................................................................. 171 10.3.3 Timer I/O Control Register (TIOR) ...................................................................... 173 10.3.4 Timer Interrupt Enable Register (TIER) ............................................................... 190 10.3.5 Timer Status Register (TSR)................................................................................. ...
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Input/Output Pins ............................................................................................................... 247 11.3 Register Descriptions ......................................................................................................... 247 11.3.1 Timer Mode Register (TMDR) ............................................................................. 248 11.3.2 Timer Control Register (TCNR) ........................................................................... 249 11.3.3 Timer Status Register (TSR)................................................................................. 250 11.3.4 Timer Counter (TCNT)......................................................................................... 250 11.3.5 Timer Buffer Registers (TBR) ...
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Sample Setup Procedure for Normal Pulse Output............................................... 293 12.4.4 Example of Normal Pulse Output (Example of Five-Phase Pulse Output)........... 294 12.4.5 Non-Overlapping Pulse Output............................................................................. 295 12.4.6 Sample Setup Procedure for Non-Overlapping Pulse Output ............................... 297 12.4.7 Example of Non-Overlapping ...
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Smart Card Mode Register (SCMR) ..................................................................... 330 14.3.9 Bit Rate Register (BRR) ....................................................................................... 331 14.4 Operation in Asynchronous Mode ..................................................................................... 338 14.4.1 Data Transfer Format............................................................................................ 338 14.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode ..................................................................................................................... 340 ...
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Notes when Switching from SCK Pin to Port Pin................................................. 381 Section 15 Controller Area Network (HCAN) ..................................................383 15.1 Features .............................................................................................................................. 383 15.2 Input/Output Pins ............................................................................................................... 385 15.3 Register Descriptions ......................................................................................................... 385 15.3.1 Master Control Register (MCR) ........................................................................... 386 15.3.2 ...
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Error Counters....................................................................................................... 431 15.8.6 Register Access..................................................................................................... 431 15.8.7 HCAN Medium-Speed Mode ............................................................................... 431 15.8.8 Register Hold in Standby Modes .......................................................................... 431 15.8.9 Usage of Bit Manipulation Instructions ................................................................ 431 15.8.10 HCAN TXCR Operation....................................................................................... 432 15.8.11 HCAN Transmit Procedure................................................................................... 433 ...
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Flash Memory Control Register 2 (FLMCR2)...................................................... 461 18.5.3 Erase Block Register 1 (EBR1) ............................................................................ 461 18.5.4 Erase Block Register 2 (EBR2) ............................................................................ 462 18.5.5 RAM Emulation Register (RAMER).................................................................... 462 18.6 On-Board Programming Modes......................................................................................... 463 18.6.1 Boot Mode ............................................................................................................ 464 ...
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Clearing Sleep Mode............................................................................................. 495 20.4 Software Standby Mode..................................................................................................... 496 20.4.1 Transition to Software Standby Mode .................................................................. 496 20.4.2 Clearing Software Standby Mode ......................................................................... 496 20.4.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode.... 497 20.4.4 Software Standby Mode ...
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Section 1 Overview Figure 1.1 Internal Block Diagram (HD64F2612, HD6432612, and HD6432611)...................... 3 Figure 1.2 Internal Block Diagram (HD6432616 and HD6432614) ............................................ 4 Figure 1.3 Pin Arrangement (HD64F2612, HD6432612, and HD6432611) ................................ 5 Figure 1.4 Pin Arrangement (HD6432616 and HD6432614)....................................................... ...
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Section 6 PC Break Controller (PBC) Figure 6.1 Block Diagram of PC Break Controller ................................................................... 90 Figure 6.2 Operation in Power-Down Mode Transitions .......................................................... 93 Section 7 Bus Controller Figure 7.1 On-Chip Memory Access Cycle............................................................................... 97 Figure 7.2 On-Chip Support ...
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Figure 10.17 Cascaded Operation Setting Procedure .................................................................. 209 Figure 10.18 Example of Cascaded Operation (1)....................................................................... 210 Figure 10.19 Example of Cascaded Operation (2)....................................................................... 210 Figure 10.20 Example of PWM Mode Setting Procedure ........................................................... 213 Figure 10.21 Example of PWM Mode ...
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Figure 11.3 MMT Canceling Procedure.................................................................................... 255 Figure 11.4 Example of TCNT Count Operation ...................................................................... 256 Figure 11.5 Examples of Counter and Register Operations....................................................... 257 Figure 11.6 Example of PWM Waveform Generation .............................................................. 260 Figure 11.7 Example of TCNT Counter Clearing ...
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Figure 14.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)................................................. 338 Figure 14.3 Receive Data Sampling Timing in Asynchronous Mode ....................................... 340 Figure 14.4 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode)............................................................................................ 341 ...
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Figure 14.34 Sample Flowchart for Mode Transition during Transmission................................ 379 Figure 14.35 Pin States during Transmission in Asynchronous Mode (Internal Clock) ............. 379 Figure 14.36 Pin States during Transmission in Clocked Synchronous Mode (Internal Clock) ...................................................................................................... 380 Figure 14.37 Sample ...
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Figure 18.6 Programming/Erasing Flowchart Example in User Program Mode....................... 467 Figure 18.7 Flowchart for Flash Memory Emulation in RAM .................................................. 468 Figure 18.8 Example of RAM Overlap Operation..................................................................... 469 Figure 18.9 Program/Program-Verify Flowchart ...................................................................... 471 Figure 18.10 Erase/Erase-Verify Flowchart ................................................................................ ...
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Section 1 Overview Table 1.1 Comparison of Product Specifications ...................................................................... 12 Section 2 CPU Table 2.1 Instruction Classification........................................................................................... 30 Table 2.2 Operation Notation.................................................................................................... 31 Table 2.3 Data Transfer Instructions ......................................................................................... 32 Table 2.4 Arithmetic Operations Instructions ........................................................................... 33 Table 2.5 ...
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Table 8.4 Register Information in Block Transfer Mode ........................................................ 117 Table 8.5 DTC Execution Status ............................................................................................. 122 Table 8.6 Number of States Required for Each Execution Status ........................................... 122 Section 9 I/O Ports Table 9.1 Port Functions ......................................................................................................... 128 Table ...
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Table 10.14 TIOR_1 (channel 1) ................................................................................................ 176 Table 10.15 TIOR_2 (channel 2) ................................................................................................ 177 Table 10.16 TIORH_3 (channel 3).............................................................................................. 178 Table 10.17 TIORL_3 (channel 3) .............................................................................................. 179 Table 10.18 TIOR_4 (channel 4) ................................................................................................ 180 Table 10.19 TIOR_5 (channel 5) ................................................................................................ ...
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Table 14.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)................... 335 Table 14.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ....................... 336 Table 14.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)....... 336 Table 14.8 ...
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Section 20 Power-Down Modes Table 20.1 Low Power Dissipation Mode Transition Conditions ............................................. 487 Table 20.2 LSI Internal States in Each Mode............................................................................ 489 Table 20.3 Oscillation Stabilization Time Settings ................................................................... 497 φ Pin State in Each Processing State ....................................................................... 501 ...
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Rev. 7.00 Sep. 11, 2009 Page xxxiv of xxxiv REJ09B0211-0700 ...
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Overview • High-speed H8S/2600 central processing unit with an internal 16-bit architecture ⎯ Upward-compatible with H8/300 and H8/300H CPUs on an object level ⎯ Sixteen 16-bit general registers ⎯ 69 basic instructions • Various peripheral functions ⎯ PC break ...
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Section 1 Overview • Compact package Package Package Code QFP-80 FP-80Q/FP-80QV Note: MMT, PPG, PC break controller, and DTC are not implemented in the H8S/2614 and H8S/2616. Rev. 7.00 Sep. 11, 2009 Page 2 of 566 REJ09B0211-0700 Body Size Pin ...
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Internal Block Diagram MD2 MD1 MD0 EXTAL XTAL PLLVCL PLLCAP PLLVSS STBY RES FWE/NC * NMI φ PF7/ PF6 PF5 PF4 PF3/ADTRG/IRQ3 PF2 PF1 PF0/IRQ2 Note: * The FWE pin is provided only in the flash memory version. The ...
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Section 1 Overview MD2 MD1 MD0 EXTAL XTAL PLLVCL PLLCAP PLLVSS STBY RES NC NMI PF7/φ PF6 PF5 PF4 PF3/ADTRG/IRQ3 PF2 PF1 PF0/IRQ2 Figure 1.2 Internal Block Diagram (HD6432616 and HD6432614) Rev. 7.00 Sep. 11, 2009 Page 4 of 566 ...
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Pin Arrangement AVcc P93/AN11 P92/AN10 P91/AN9 P90/AN8 P47/AN7 P46/AN6 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 AVss P10/PO8/TIOCA0 Vcc P11/PO9/TIOCB0 Vss P12/PO10/TIOCC0/TCLKA VCL Note: * The FWE pin is used only in the flash memory version. The NC pin is ...
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Section 1 Overview AVcc 61 P93/AN11 62 P92/AN10 63 P91/AN9 64 P90/AN8 65 P47/AN7 66 P46/AN6 67 P45/AN5 68 P44/AN4 69 P43/AN3 70 P42/AN2 71 P41/AN1 72 P40/AN0 73 AVss 74 P10/TIOCA0 75 Vcc 76 P11/TIOCB0 77 Vss 78 P12/TIOCC0/TCLKA ...
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Pin Functions Type Symbol Pin NO. Power VCC 27 Supply 48 76 VSS VCL 52 80 Clock PLLVCL 44 PLLVSS 46 PLLCAP 42 XTAL 47 EXTAL 49 φ 15 Operating MD2 40 mode MD1 39 control ...
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Section 1 Overview Type Symbol Pin NO. Interrupts NMI 43 IRQ5 21 IRQ4 18 IRQ3 11 IRQ2 8 IRQ1 4 IRQ0 2 16-bit TCLKA 79 timer-pulse TCLKB 1 unit TCLKC 3 TCLKD 5 TIOCA0 75 TIOCB0 77 TIOCC0 79 TIOCD0 ...
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Type Symbol Pin NO. Motor PUOA 28 manage- ment timer PUOB 29 (MMT) PVOA 30 PVOB 31 PWOA 32 PWOB 33 PCI 24 PCO 26 POE3 37 POE2 36 POE1 35 POE0 34 Serial TxD2 35 communi- TxD1 19 cation ...
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Section 1 Overview Type Symbol Pin NO. A/D AN11 62 converter AN10 63 AN9 64 AN8 65 AN7 66 AN6 67 AN5 68 AN4 69 AN3 70 AN2 71 AN1 72 AN0 73 ADTRG 11 AVCC 61 AVSS 74 I/O ...
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Type Symbol Pin NO. I/O ports PA3 37 PA2 36 PA1 35 PA0 34 PB7 33 PB6 32 PB5 31 PB4 30 PB3 29 PB2 28 PB1 26 PB0 24 PC7 23 PC6 22 PC5 21 PC4 20 PC3 19 ...
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Section 1 Overview 1.5 Differences between H8S/2612, H8S/2611, H8S/2614, and H8S/2616 The amount of on-chip ROM and the specific on-chip modules implemented differ among the H8S/2612, H8S/2611, H8S/2614, and H8S/2616. Table 1.1 lists the specifications for these products. Note: The ...
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The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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Section 2 CPU ⎯ 16 × 16-bit register-register multiply: ⎯ 32 ÷ 16-bit register-register divide: • Two CPU operating modes ⎯ Normal mode * ⎯ Advanced mode • Power-down state ⎯ Transition to power-down state by SLEEP instruction ⎯ CPU ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements: • More general registers and control registers ⎯ Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been ...
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Section 2 CPU 2.2 CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the ...
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H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Figure 2.1 Exception Vector Table (Normal Mode) SP (16 bits) (a) Subroutine Branch Notes: 1. When EXR is not used it is not stored on the stack. 2. ...
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Section 2 CPU • Instruction Set All instructions and addressing modes can be used. • Exception Vector Table and Memory Indirect Branch Addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table in ...
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Stack Structure In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they ...
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Section 2 CPU 2.3 Address Space Figure 2.5 shows a memory map for the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in ...
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Register Configuration The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), ...
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Section 2 CPU 2.4.1 General Registers The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a ...
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SP (ER7) 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When ...
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Section 2 CPU 2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the ...
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Bit Bit Name Initial Value undefined 5 H undefined 4 U undefined 3 N undefined 2 Z undefined 1 V undefined R/W Description R/W Interrupt Mask Bit Masks interrupts other than NMI when set to ...
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Section 2 CPU Bit Bit Name Initial Value 0 C undefined 2.4.5 Multiply-Accumulate Register (MAC) This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32- bit registers denoted MACH and MACL. The lower 10 bits of ...
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Data Formats The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. ...
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Section 2 CPU Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register ...
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Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, however word or longword data must begin at an even address attempt is made ...
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Section 2 CPU 2.6 Instruction Set The H8S/2600 CPU has 69 instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV POP * , PUSH * 1 LDM, STM MOVFPE * ...
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Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.2 Operation Notation Symbol Description General register (destination ...
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Section 2 CPU Table 2.3 Data Transfer Instructions Size * Instruction Function (EAs) → Rd, Rs → (EAd) MOV B/W/L Moves data between two general registers or between a general register and memory, or moves immediate data to a general ...
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Table 2.4 Arithmetic Operations Instructions Size * Instruction Function Rd ± Rs → Rd, Rd ± #IMM → Rd ADD B/W/L SUB Performs addition or subtraction on data in two general registers immediate data and data in a ...
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Section 2 CPU Size * 1 Instruction Function Rd ÷ Rs → Rd DIVXS B/W Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ ...
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Table 2.5 Logic Operations Instructions Size * Instruction Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd AND B/W/L Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs ...
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Section 2 CPU Table 2.7 Bit Manipulation Instructions Size * Instruction Function 1 → (<bit-No.> of <EAd>) BSET B Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate ...
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Size * Instruction Function C ⊕ (<bit-No.> of <EAd>) → C BXOR B XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. C ⊕ ¬ (<bit-No.> ...
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Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) ...
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Table 2.9 System Control Instructions Size * Instruction Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR LDC B/W Moves ...
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Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function if R4L ≠ 0 then EEPMOV.B — else next ≠ 0 then EEPMOV.W — else next; Transfers a data block. Starting from the address set in ...
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Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. ...
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Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct ...
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Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of ...
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Section 2 CPU Table 2.12 Absolute Address Access Ranges Absolute Address Data address 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction 24 bits (@aa:24) address Note: * Normal mode is not available in this LSI. 2.7.6 Immediate—#xx:8, ...
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Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling odd address is specified in word or longword memory access branch ...
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Section 2 CPU Table 2.13 Effective Address Calculation Addressing Mode and Instruction Format Register direct (Rn) Register indirect (@ERn) Register indirect with post-increment or pre-decrement • Register indirect with post-increment @ERn+ • Register indirect with pre-decrement @−ERn Rev. 7.00 Sep. ...
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Addressing Mode and Instruction Format Absolute address Immediate Note: * Normal mode is not available in this LSI. Effective Address Calculation PC contents Sign extension Memory contents Memory contents Rev. 7.00 Sep. 11, 2009 Page 47 of 566 Section 2 ...
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Section 2 CPU 2.8 Processing States The H8S/2600 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.13 indicates ...
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Exception handling state Request for End of exception exception handling handling Program execution state Notes: From any state, a transition to hardware standby mode occurs when STBY goes low. * From any state except hardware standby mode, a transition to ...
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Section 2 CPU Rev. 7.00 Sep. 11, 2009 Page 50 of 566 REJ09B0211-0700 ...
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Section 3 MCU Operating Modes 3.1 Operating Mode Selection This LSI supports only operating mode 7, that is, the advanced single-chip mode. The operating mode is determined by the setting of the mode pins (MD2 to MD0). Only mode 7 ...
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Section 3 MCU Operating Modes 3.2.1 Mode Control Register (MDCR) Bit Bit Name Intial Value 7 — — All 0 2 MDS2 — 1 MDS1 — 0 MDS0 — Rev. 7.00 Sep. 11, 2009 Page 52 ...
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System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that selects saturating or non-saturating calculation for the MAC instruction, selects the interrupt control mode and the detected edge for NMI, and enables or disables on-chip RAM. Bit Bit ...
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Section 3 MCU Operating Modes 3.3 Pin Functions in Each Operating Mode The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, however external addresses cannot be accessed. All I/O ports are available for ...
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Address Map Figure 3.1 shows the address map in each operating mode. H8S/2612, H8S/2616 ROM: 128 kbytes, RAM: 4 kbytes Mode 7 Advanced single-chip mode H'000000 On-chip ROM (F-ZTAT/mask ROM * ) H'01FFFF H'FFE000 On-chip RAM H'FFEFBF H'FFF800 On-chip ...
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Section 3 MCU Operating Modes Rev. 7.00 Sep. 11, 2009 Page 56 of 566 REJ09B0211-0700 ...
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Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions ...
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Section 4 Exception Handling Table 4.2 Exception Handling Vector Table Exception Source Power-on reset Manual reset * 2 Reserved for system use Trace Interrupt (direct transitions Interrupt (NMI) Trap instruction (#0) (#1) (#2) (#3) Reserved for system use ...
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Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ...
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Section 4 Exception Handling φ RES Internal address bus Internal read signal Internal write signal Internal data bus (1)(3) Reset exception handling vector address(when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ...
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RES Address bus RD HWR, LWR D15 to D0 (1)(3) Reset exception handling vector address(when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note: * Three ...
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Section 4 Exception Handling 4.4 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section ...
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Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. Trap instruction exception handling is conducted as follows: 1. The values ...
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Section 4 Exception Handling 4.7 Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. (a) Normal Modes (b) Advanced Modes Notes: 1. Ignored on return. 2. Normal modes ...
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Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack ...
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Section 4 Exception Handling Rev. 7.00 Sep. 11, 2009 Page 66 of 566 REJ09B0211-0700 ...
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Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes ⎯ Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with IPR ...
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Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1. INTM1, INTM0 SYSCR NMIEG NMI input IRQ input Internal interrupt request SWDTEND to TEI2 Interrupt controller Legend: IRQ sense control register ISCR: IRQ enable ...
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Input/Output Pins Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Pin Configuration Name I/O NMI Input IRQ5 Input IRQ4 Input IRQ3 Input IRQ2 Input IRQ1 Input IRQ0 Input 5.3 Register Descriptions The interrupt controller has the ...
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Section 5 Interrupt Controller 5.3.1 Interrupt Priority Registers (IPRA to IPRH,IPRJ, IPRK, IPRM) The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels for interrupts other than NMI. The ...
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IRQ Enable Register (IER) IER is an 8-bit readable/writable register that controls the enabling and disabling of interrupt requests IRQ0 to IRQ5. Bit Bit Name Initial Value − All 0 5 IRQ5E 0 4 IRQ4E 0 3 ...
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Section 5 Interrupt Controller Bit Bit Name Initial Value − All IRQ5SCB 0 10 IRQ5SCA 0 9 IRQ4SCB 0 8 IRQ4SCA 0 7 IRQ3SCB 0 6 IRQ3SCA 0 Rev. 7.00 Sep. 11, 2009 Page 72 ...
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Bit Bit Name Initial Value 5 IRQ2SCB 0 4 IRQ2SCA 0 3 IRQ1SCB 0 2 IRQ1SCA 0 1 IRQ0SCB 0 0 IRQ0SCA 0 R/W Description R/W IRQ2 Sense Control B R/W IRQ2 Sense Control A 00: Interrupt request generated at ...
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Section 5 Interrupt Controller 5.3.4 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ0 to IRQ5 interrupt requests. Bit Bit Name Initial Value − All 0 5 IRQ5F 0 4 IRQ4F ...
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Interrupt 5.4.1 External Interrupts There are seven external interrupts: NMI and IRQ0 to IRQ5. These interrupts can be used to restore this LSI from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by ...
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Section 5 Interrupt Controller 5.4.2 Internal Interrupts The sources for internal interrupts from on-chip supporting modules have the following features: • For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select ...
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Table 5.2 Interrupt Sources, Vector Addresses, and Interrupt Priorities Interrupt Origin of Source Interrupt Source External NMI pin IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 — Reserved for system use Reserved for system use DTC SWDTEND Watchdog WOVI0 timer 0 PC ...
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Section 5 Interrupt Controller Interrupt Origin of Source Interrupt Source TPU TGID_3 channel 3 TCIV_3 TPU TGIA_4 channel 4 TGIB_4 TCIV_4 TCIU_4 TPU TGIA_5 channel 5 TGIB_5 TCIV_5 TCIU_5 SCI ERI_0 channel 0 RXI_0 TXI_0 TEI_0 SCI ERI_1 channel 1 ...
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Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by SYSCR. Table ...
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Section 5 Interrupt Controller 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table. IRQ0 Figure ...
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Interrupt Control Mode 2 In interrupt control mode 2, mask control is applied to eight levels for interrupt requests other than NMI by comparing the EXR interrupt mask level ( bits) in the CPU and the IPR ...
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Section 5 Interrupt Controller Level 7 interrupt? Yes Mask level 6 or below? Yes Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2 Rev. 7.00 Sep. 11, 2009 Page 82 of 566 REJ09B0211-0700 Program execution status ...
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Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip ...
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Section 5 Interrupt Controller Figure 5.5 Interrupt Exception Handling Rev. 7.00 Sep. 11, 2009 Page 84 of 566 REJ09B0211-0700 ...
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Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained ...
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Section 5 Interrupt Controller Table 5.5 Number of States in Interrupt Handling Routine Execution Status Symbol Instruction fetch S I Branch address read S J Stack manipulation S K Legend: M: Number of wait states in an external device access. ...
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Internal address bus Internal write signal TCIEV TCFV TCIV interrupt signal Figure 5.6 Contention between Interrupt Generation and Disabling 5.7.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these ...
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Section 5 Interrupt Controller 5.7.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the ...
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Section 6 PC Break Controller (PBC) The PC break controller (PBC) provides functions that simplify program debugging. Using these functions easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an ...
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Section 6 PC Break Controller (PBC) BARA Comparator Internal address Access status Comparator BARB Figure 6.1 Block Diagram of PC Break Controller 6.2 Register Descriptions The PC break controller has the following registers. For details on register addresses and register ...
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Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 6.2.3 Break Control Register A (BCRA) BCRA controls channel A PC breaks. BCRA also contains a condition ...
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Section 6 PC Break Controller (PBC) 6.2.4 Break Control Register B (BCRB) BCRB is the channel B break control register. The bit configuration is the same as for BCRA. 6.3 Operation The operation flow from break condition setting to PC ...
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Notes on PC Break Interrupt Handling • When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction PC break exception handling is executed after all data transfers have been completed and the EEPMOV.B instruction ...
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Section 6 PC Break Controller (PBC) 6.3.5 When Instruction Execution is Delayed by One State While the break interrupt enable bit is set to 1, instruction execution is one state later than usual. • For 1-word branch instructions (Bcc d:8, ...
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Usage Notes 6.4.1 Module Stop Mode Setting PBC operation can be disabled or enabled using the module stop control register. The initial setting is for PBC operation to be halted. Register access is enabled by clearing module stop mode. ...
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Section 6 PC Break Controller (PBC) 6.4.7 PC Break Set for Instruction Fetch at Address Following Bcc Instruction When a PC break is set for an instruction fetch at an address following a Bcc instruction break interrupt is ...
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Section 7 Bus Controller The H8S/2600 CPU is driven by a system clock, denoted by the symbol ø. The bus controller controls a memory cycle and a bus cycle. Different methods are used to access on-chip memory and on-chip support ...
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Section 7 Bus Controller 7.1.2 On-Chip Support Module Access Timing The on-chip support modules, except for HCAN, MMT, and POE, are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular ...
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On-Chip HCAN Module Access Timing On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait states can be inserted by means of a wait request from the HCAN. On-chip HCAN module access ...
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Section 7 Bus Controller 7.1.4 On-Chip MMT Module Access Timing On-chip MMT module and POE access are performed in three states. The data width is 16 bits. On-chip MMT module access timings are shown in figure 7.4. φ Internal address ...
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Bus Arbitration The Bus Controller has a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and DTC, which perform read/write operations when they control the bus. Note: No DTC is implemented in the ...
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Section 7 Bus Controller Rev. 7.00 Sep. 11, 2009 Page 102 of 566 REJ09B0211-0700 ...
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Section 8 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 8.1 shows a block diagram of the DTC. The DTC’s register information ...
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Section 8 Data Transfer Controller (DTC) Interrupt controller Interrupt request CPU interrupt request Legend: MRA, MRB: CRA, CRB: SAR: DAR: DTCERA to DTCERG: DTVECR: Rev. 7.00 Sep. 11, 2009 Page 104 of 566 REJ09B0211-0700 Internal address bus DTC Internal data ...
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Register Configuration The DTC has the following registers. • DTC mode register A (MRA) • DTC mode register B (MRB) • DTC source address register (SAR) • DTC destination address register (DAR) • DTC transfer count register A (CRA) ...
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Section 8 Data Transfer Controller (DTC) 8.2.1 DTC Mode Register A (MRA) MRA is an 8-bit register that selects the DTC operating mode. Bit Bit Name Initial Value 7 SM1 Undefined 6 SM0 Undefined 5 DM1 Undefined 4 DM0 Undefined ...
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DTC Mode Register B (MRB) MRB is an 8-bit register that selects the DTC operating mode. Bit Bit Name Initial Value 7 CHNE Undefined 6 DISEL Undefined 5 to — Undefined 0 8.2.3 DTC Source Address Register (SAR) SAR ...
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Section 8 Data Transfer Controller (DTC) functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. 8.2.6 DTC Transfer ...
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DTC Vector Register (DTVECR) DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. Bit Bit Name Initial Value 7 SWDTE 0 6 DTVEC6 0 ...
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Section 8 Data Transfer Controller (DTC) Source flag cleared On-chip supporting module IRQ interrupt Interrupt request DTVECR Figure 8.2 Block Diagram of DTC Activation Source Control 8.4 Location of Register Information and DTC Vector Table Locate the register information in ...
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Register MRA information start address MRB Chain transfer MRA MRB Figure 8.3 Correspondence between DTC Vector Address and Register Information Section 8 Data Transfer Controller (DTC) Lower address SAR DAR CRA CRB SAR DAR CRA CRB ...
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Section 8 Data Transfer Controller (DTC) Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Interrupt Origin of Source Interrupt Source Software Write to DTVECR External pin IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 Reserved for System use A/D ADI ...
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Interrupt Origin of Source Interrupt Source Reserved for — system use SCI RXI_0 channel 0 TXI_0 SCI RXI_1 channel 1 TXI_1 SCI RXI_2 channel 2 TXI_2 HCAN Reserved for system use RM0 Reserved for system use MMT TGIMN TGINN — ...
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Section 8 Data Transfer Controller (DTC) 8.5 Operation Register information is stored in on-chip memory. When activated, the DTC reads register information in on-chip memory and transfers data. After the data transfer, the DTC writes updated register information back to ...
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Normal Mode In normal mode, one operation transfers one byte or one word of data. Table 8.2 lists the register information in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ...
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Section 8 Data Transfer Controller (DTC) 8.5.2 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. Table 8.3 lists the register information in repeat mode. From 1 to 256 transfers can be specified. Once ...
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Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 8.4 lists the register information in block transfer mode. The ...
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Section 8 Data Transfer Controller (DTC) First block SAR or DAR Nth block Figure 8.7 Memory Mapping in Block Transfer Mode Rev. 7.00 Sep. 11, 2009 Page 118 of 566 REJ09B0211-0700 Block area Transfer DAR or SAR ...
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Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can ...
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Section 8 Data Transfer Controller (DTC) 8.5.5 Interrupts An interrupt request is issued to the CPU when the DTC has completed the specified number of data transfers data transfer for which the DISEL bit was set to 1. ...
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DTC activation request DTC request Address Figure 8.10 DTC Operation Timing (Example of Block Transfer Mode, φ DTC activation request DTC request Vector read Address Figure 8.11 DTC Operation Timing (Example of Chain Transfer) 8.5.7 Number of DTC Execution ...
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Section 8 Data Transfer Controller (DTC) Table 8.5 DTC Execution Status Vector Read Mode I Normal 1 Repeat 1 Block transfer 1 Legend: N: Block size (initial setting of CRAH and CRAL) Table 8.6 Number of States Required for Each ...
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Procedures for Using DTC 8.6.1 Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in on-chip RAM. 2. Set the start ...
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Section 8 Data Transfer Controller (DTC) 2. Set the start address of the register information at the DTC vector address. 3. Set the corresponding bit in DTCER Set the SCI to the appropriate receive mode. Set the ...
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Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and NDER for which output performed to 1. Using PCR, select the TPU compare match to be used ...
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Section 8 Data Transfer Controller (DTC) 8.8 Usage Notes 8.8.1 Module Stop Mode Setting DTC operation can be disabled or enabled using the module stop control register. The initial setting is for DTC operation to be halted. Register access is ...
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Table 9.1 summarizes the port functions. The pins of each port also have other functions such as input/output or interrupt input pins of on-chip supporting modules. Each I/O port includes a data direction register (DDR) that controls input/output, a data ...
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Section 9 I/O Ports Table 9.1 Port Functions Port Description Port 1 General I/O port also functioning as TPU I/O pins, PPG output pins, and interrupt input pins Note: The H8S/2614 and H8S/2616 have no PPG outputs. Port 4 General ...
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Port Description Port B General I/O port also functioning as TPU_5, TPU_4, and TPU_3 I/O pins, and MMT I/O pins Note: The H8S/2614 and H8S/2616 have no MMT input and output pins. Port C General I/O port also functioning as ...
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Section 9 I/O Ports 9.1 Port 1 Port 8-bit I/O port and has the following registers. For details on register addresses and register states during each process, refer to appendix A, On-Chip I/O Register. • Port 1 ...
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Port 1 Data Register (P1DR) P1DR is an 8-bit readable/writable register that stores output data for port 1 pins. Bit Bit Name Initial Value 7 P17DR 0 6 P16DR 0 5 P15DR 0 4 P14DR 0 3 P13DR 0 ...
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Section 9 I/O Ports 9.1.4 Pin Functions Port 1 pins also function as TPU I/O pins, PPG output pins, and interrupt input pins. The correspondence between the register specification and the pin functions is shown below. Note: The H8S/2614 and ...
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Table 9.4 P15 Pin Function TPU Channel Output 1 Setting * P15DDR — NDER13 — Pin function TIOCB1 output Note: * For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU). Table 9.5 P14 ...
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Section 9 I/O Ports Table 9.7 P12 Pin Function TPU Channel Output 0 Setting * P12DDR — NDER10 — Pin function TIOCC0 output Note: * For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit ...
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Port 4 Port 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins. For details on register addresses, refer to appendix A, On-Chip I/O Register. • Port 4 register (PORT4) 9.2.1 Port ...
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Section 9 I/O Ports 9.3 Port 9 Port 4-bit input-only port. Port 9 pins also function as A/D converter analog input pins. Port 9 has the following registers. For details on register addresses, refer to appendix A, ...
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Port A Port 4-bit I/O port that also has other functions. Port A has the following registers. For details on register addresses and register states during each processing, refer to appendix A, On- Chip I/O Register. ...
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Section 9 I/O Ports 9.4.2 Port A Data Register (PADR) PADR is an 8-bit readable/writable register that stores output data for port A pins. Bit Bit Name Initial Value 7 — Undefined 6 — Undefined 5 — Undefined 4 — ...
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Port A Pull-Up MOS Control Register (PAPCR) PAPCR is an 8-bit register that controls the MOS input pull-up function. Bit Bit Name Initial Value 7 — Undefined 6 — Undefined 5 — Undefined 4 — Undefined 3 PA3PCR 0 ...
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Section 9 I/O Ports 9.4.6 Pin Functions Port A pins also function as SCI_2 I/O, interrupt input, and POE input pins. The correspondence between the register specification and the pin functions is shown below. Note: The H8S/2614 and H8S/2616 have ...
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Port B Port 8-bit I/O port that also has other functions. Port B has the following registers. For details on register addresses and register states during each processing, refer to appendix A, On- Chip I/O Register. ...
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Section 9 I/O Ports 9.5.2 Port B Data Register (PBDR) PBDR is an 8-bit readable/writable register that stores output data for the port B pins. Bit Bit Name Initial Value 7 PB7DR 0 6 PB6DR 0 5 PB5DR 0 4 ...
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Port B Pull-Up MOS Control Register (PBPCR) PBPCR is an 8-bit read/write register that controls the on/off state of MOS input pull-up of port B. Bit Bit Name Initial Value 7 PB7PCR 0 6 PB6PCR 0 5 PB5PCR 0 ...
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Section 9 I/O Ports 9.5.6 Pin Functions Port B pins also function as TPU and MMT I/O pins. The correspondence between the register specification and the pin functions is shown below. Note: The H8S/2614 and H8S/2616 have no MMT input ...
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Table 9.16 PB5 Pin Function PVOBE TPU channel 4 Output setting * PB5DDR — Pin function TIOCB4 output Note: * For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU). Table 9.17 PB4 Pin ...
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Section 9 I/O Ports Table 9.19 PB2 Pin Function PUOAE TPU channel 3 Output setting * PB2DDR — Pin function TIOCC3 output Note: * For details on the TPU channel specification, refer to section 10, 16-Bit Timer Pulse Unit (TPU). ...
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Port C Port 8-bit I/O port that also has other functions. Port C has the following registers. For details on register addresses and register states during each processing, refer to appendix A, On- Chip I/O Register. ...
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Section 9 I/O Ports 9.6.2 Port C Data Register (PCDR) PCDR is an 8-bit readable/writable register that stores output data for the port C pins. Bit Bit Name Initial Value 7 PC7DR 0 6 PC6DR 0 5 PC5DR 0 4 ...
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Port C Pull-Up MOS Control Register (PCPCR) PCPCR is an 8-bit read/write register that controls the on/off state of MOS input pull-up of port C. Bit Bit Name Initial Value 7 PC7PCR 0 6 PC6PCR 0 5 PC5PCR 0 ...
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Section 9 I/O Ports 9.6.6 Pin Functions Port C pins also function as SCI_1 and SCI_0 I/O and interrupt input. The correspondence between the register specification and the pin functions is shown below. PC7: This pin function is switched as ...
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PC3/TxD1: The pin function is switched as shown below according to the operating mode, bit TE in the SCI1’s SCR, and bit PC3DDR. TE PC3DDR 0 Pin function PC3 input PC2/SCK0/IRQ4: The pin function is switched as shown below according ...
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Section 9 I/O Ports 9.7 Port D Port 8-bit I/O port that also has other functions. Port D has the following registers. For details on register addresses and register states during each processing, refer to appendix A, ...
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Port D Data Register (PDDR) PDDR is an 8-bit readable/writable register that stores output data for the port D pins. Bit Bit Name Initial Value 7 PD7DR 0 6 PD6DR 0 5 PD5DR 0 4 PD4DR 0 3 PD3DR ...
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Section 9 I/O Ports 9.7.4 Port D Pull-Up MOS Control Register (PDPCR) PDPCR is an 8-bit readable/writable register that controls on/off states of the input pull-up MOS of port D. Bit Bit Name Initial Value 7 PD7PCR 0 6 PD6PCR ...
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Port F Port 8-bit I/O port that also has other functions. Port F has the following registers. For details on register addresses and register states during each processing, refer to appendix A, On- Chip I/O Register. ...
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Section 9 I/O Ports 9.8.2 Port F Data Register (PFDR) PFDR is an 8-bit readable/writable register that stores output data for the port F pins. Bit Bit Name Initial Value 7 — PF6DR 0 5 PF5DR 0 4 ...
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Pin Functions Port 8-bit I/O port. Port F pins also function as external interrupt input, IRQ2 and IRQ3, A/D trigger input (ADTRG), and system clock output (φ). φ PF7/ : The pin function is switched as ...
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Section 9 I/O Ports PF2: The pin function is switched as shown below according to bit PF2DDR. PF2DDR Pin function PF1: The pin function is switched as shown below according to bit PF1DDR. PF1DDR Pin function PF0/IRQ2: The pin function ...
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Section 10 16-Bit Timer Pulse Unit (TPU) This LSI has an on-chip 16-bit timer pulse unit (TPU) comprised of six 16-bit timer channels. The function list of the 16-bit timer unit and its block diagram are shown in table 10.1 ...
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Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.1 TPU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 φ/1 Count clock φ/4 φ/16 φ/64 TCLKA TCLKB TCLKC TCLKD General registers TGRA_0 TGRB_0 General registers/ ...
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Item Channel 0 Channel 1 DTC TGR TGR activation compare compare match or match or input capture input capture A/D TGRA_0 TGRA_1 converter compare compare trigger match or match or input capture input capture PPG TGRA_0/ TGRA_1/ trigger TGRB_0 TGRB_1 ...
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Section 10 16-Bit Timer Pulse Unit (TPU) Input/output pins Channel 3: TIOCA3 TIOCB3 TIOCC3 TIOCD3 Channel 4: TIOCA4 TIOCB4 Channel 5: TIOCA5 TIOCB5 Clock input φ/1 Internal clock: φ/4 φ/16 φ/64 φ/256 φ/1024 φ/4096 External clock: TCLKA TCLKB TCLKC TCLKD ...
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Input/Output Pins Table 10.2 TPU Pins Channel Symbol I/O All TCLKA Input TCLKB Input TCLKC Input TCLKD Input 0 TIOCA0 I/O TIOCB0 I/O TIOCC0 I/O TIOCD0 I/O 1 TIOCA1 I/O TIOCB1 I/O 2 TIOCA2 I/O TIOCB2 I/O 3 TIOCA3 ...
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Section 10 16-Bit Timer Pulse Unit (TPU) 10.3 Register Descriptions The TPU has the following registers. For details on register addresses and register states during each process, refer to appendix A, On-Chip I/O Register. To distinguish registers in each channel, ...