MC68HC711E9CFNE3 Freescale Semiconductor, MC68HC711E9CFNE3 Datasheet - Page 203

IC MCU 3MHZ 12K OPT 52-PLCC

MC68HC711E9CFNE3

Manufacturer Part Number
MC68HC711E9CFNE3
Description
IC MCU 3MHZ 12K OPT 52-PLCC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711E9CFNE3

Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
12KB (12K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Processor Series
HC711E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Allowing for Bootstrap Mode
After the MCU sends $FF [8], it enters the WAIT1 loop [9] and waits for the first data character from the
host. When this character is received [10], the MCU programs it into the address pointed to by the Y index
register. When the programming time delay is over, the MCU reads the programmed data, transmits it to
the host for verification [11], and returns to the top of the WAIT1 loop to wait for the next data character
[12]. Because the host previously sent the second data character, it is already waiting in the SCI receiver
of the MCU. Steps [13], [14], and [15] correspond to the second pass through the WAIT1 loop.
Back in the host, the first verify character is received, and the third data character is sent [6]. The host
then waits for the second verify character [7] to come back from the MCU. The sequence continues as
long as the host continues to send data to the MCU. Since the WAIT1 loop in the PROGRAM utility is an
indefinite loop, reset is used to end the process in the MCU after the host has finished sending data to be
programmed.
Allowing for Bootstrap Mode
Since bootstrap mode requires few connections to the MCU, it is easy to design systems that
accommodate bootstrap mode.
Bootstrap mode is useful for diagnosing or repairing systems that have failed due to changes in the
CONFIG register or failures of the expansion address/data buses, (rendering programs in external
memory useless). Bootstrap mode can also be used to load information into the EPROM or EEPROM of
an M68HC11 after final assembly of a module. Bootstrap mode is also useful for performing system
checks and calibration routines. The following paragraphs explain system requirements for use of
bootstrap mode in a product.
Mode Select Pins
It must be possible to force the MODA and MODB pins to logic 0, which implies that these two pins should
be pulled up to V
through resistors rather than being tied directly to V
. If mode pins are connected
DD
DD
directly to V
, it is not possible to force a mode other than the one the MCU is hard wired for. It is also
DD
good practice to use pulldown resistors to V
rather than connecting mode pins directly to V
because
SS
SS
it is sometimes a useful debug aid to attempt reset in modes other than the one the system was primarily
designed for. Physically, this requirement sometimes calls for the addition of a test point or a wire
connected to one or both mode pins. Mode selection only uses the mode pins while RESET is active.
RESET
It must be possible to initiate a reset while the mode select pins are held low. In systems where there is
no provision for manual reset, it is usually possible to generate a reset by turning power off and back on.
RxD Pin
It must be possible to drive the PD0/RxD pin with serial data from a host computer (or another MCU). In
many systems, this pin is already used for SCI communications; thus no changes are required.
M68HC11 Bootstrap Mode, Rev. 1.1
Freescale Semiconductor
203

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