MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 135

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M68HC11E Family — Rev. 3.2
MOTOROLA
NOTE:
Address:
DDRA7 — Data Direction for Port A Bit 7
Even when port A bit 7 is configured as an output, the pin still drives the
input to the pulse accumulator.
PAEN — Pulse Accumulator System Enable Bit
PAMOD — Pulse Accumulator Mode Bit
PEDGE — Pulse Accumulator Edge Control Bit
DDRA3 — Data Direction for Port A Bit 3
I4/O5 — Input Capture 4/Output Compare 5 Bit
RTR[1:0] — RTI Interrupt Rate Select Bits
Reset:
Read:
Figure 6-2. Pulse Accumulator Control Register (PACTL)
Write:
Overridden if an output compare function is configured to control the
PA7 pin
The pulse accumulator uses port A bit 7 as the PAI input, but the pin
can also be used as general-purpose I/O or as an output compare.
Refer to
Refer to
Refer to
This bit is overridden if an output compare function is configured to
control the PA3 pin.
Refer to
Refer to
0 = Input
1 = Output
0 = Input
1 = Output
DDRA7
$1026
Bit 7
0
Parallel Input/Output (I/O) Ports
Section 9. Timing
Section 9. Timing
Section 9. Timing
Section 9. Timing
Section 9. Timing
PAEWN
6
0
PAMOD
5
0
System.
System.
System.
System.
System.
PEDGE
4
0
DDRA3
3
0
Parallel Input/Output (I/O) Ports
I4/O5
2
0
RTR1
1
0
Technical Data
RTR0
Bit 0
Port A
0
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