MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 137

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

M68HC11E Family — Rev. 3.2
MOTOROLA
Address:
Address:
PORTCL is used in the handshake clearing mechanism. When an active
edge occurs on the STRA pin, port C data is latched into the PORTCL
register. Reads of this register return the last value latched into PORTCL
and clear STAF flag (following a read of PIOC with STAF set).
DDRC[7:0] — Port C Data Direction Bits
Reset:
Reset:
Read:
Read:
Write:
Write:
In handshake output mode, DDRC bits select the 3-stated output
option (DDCx = 1).
0 = Input
1 = Output
DDRC7
$1005
$1007
Figure 6-6. Port C Data Direction Register (DDRC)
PCL7
Bit 7
Bit 7
0
Figure 6-5. Port C Latched Register (PORTCL)
Parallel Input/Output (I/O) Ports
DDRC6
PCL6
6
6
0
DDRC5
PCL5
5
5
0
Indeterminate after reset
DDRC4
PCL4
4
4
0
DDRC3
PCL3
3
3
0
Parallel Input/Output (I/O) Ports
DDRC2
PCL2
2
2
0
DDRC1
PCL1
1
1
0
Technical Data
DDRC0
PCL0
Bit 0
Bit 0
Port C
0
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