MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 217

• Manufacturer Part Number: MC68HC711E9CFNE2
• Description: IC MCU 8BIT 512RAM 52-PLC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711E9CFNE2

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 2MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 38
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: OTP
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Processor Series: HC711E
• Core: HC11
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 2 MHz
• Number Of Programmable I/os: 38
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.8 Multiple-Channel Operation
10.9 Operation in Stop and Wait Modes
M68HC11E Family — Rev. 3.2
MOTOROLA
The two types of multiple-channel operation are:
If a conversion sequence is in progress when either the stop or wait
mode is entered, the conversion of the current channel is suspended.
When the MCU resumes normal operation, that channel is resampled
and the conversion sequence is resumed. As the MCU exits wait mode,
the A/D circuits are stable and valid results can be obtained on the first
conversion. However, in stop mode, all analog bias currents are disabled
and it is necessary to allow a stabilization period when leaving stop
mode. If stop mode is exited with a delay (DLY = 1), there is enough time
for these circuits to stabilize before the first conversion. If stop mode is
exited with no delay (DLY bit in OPTION register = 0), allow 10 ms for
the A/D circuitry to stabilize to avoid invalid results.
1. When SCAN = 0, a selected group of four channels is converted
2. When SCAN = 1, conversions continue to be performed on the
one time each. The first result is stored in A/D result register 1
(ADR1), and the fourth result is stored in ADR4. After the fourth
conversion is complete, all conversion activity is halted until a new
conversion command is written to the ADCTL register.
selected group of channels with the fifth conversion being stored
in register ADR1 (replacing the earlier conversion result for the
first channel in the group), the sixth conversion overwriting ADR2,
and so on.
Analog-to-Digital (A/D) Converter
Analog-to-Digital (A/D) Converter
Multiple-Channel Operation
Technical Data
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