MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 219

IC MCU 8BIT 512RAM 52-PLC

MC68HC711E9CFNE2

Manufacturer Part Number
MC68HC711E9CFNE2
Description
IC MCU 8BIT 512RAM 52-PLC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC711E9CFNE2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
12KB (12K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Processor Series
HC711E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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M68HC11E Family — Rev. 3.2
MOTOROLA
NOTE:
When the multiple-channel continuous scan mode is used, extra care is
needed in the design of circuitry driving the A/D inputs. The charge on
the capacitive DAC array before the sample time is related to the voltage
on the previously converted channel. A charge share situation exists
between the internal DAC capacitance and the external circuit
capacitance. Although the amount of charge involved is small, the rate
at which it is repeated is every 64 s for an E clock of 2 MHz. The RC
charging rate of the external circuit must be balanced against this charge
sharing effect to avoid errors in accuracy. Refer to M68HC11 Reference
Manual, Motorola document order number M68HC11RM/AD, for further
information.
CD:CA — Channel Selects D:A Bits
a conversion on each of four channels where each result register
corresponds to one channel.
Refer to
(MULT = 1), the two least significant channel select bits (CB and CA)
have no meaning and the CD and CC bits specify which group of four
channels is to be converted.
Analog-to-Digital (A/D) Converter
Channel Select
Table
CD:CC:CB:CA
Table 10-2. A/D Converter Channel Selection
1. Used for factory testing
Control Bits
10XX
0000
0001
0010
0100
0101
0011
0110
0111
1100
1101
1110
1111
10-2. When a multiple channel mode is selected
Channel Signal
Reserved
Reserved
(V
V
V
RH
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
RH
RL
)/2
(1)
(1)
(1)
(1)
Analog-to-Digital (A/D) Converter
Result in ADRx
if MULT = 1
A/D Control/Status Register
ADR1
ADR2
ADR3
ADR4
ADR1
ADR2
ADR3
ADR4
ADR1
ADR2
ADR3
ADR4
Technical Data
219

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