MC68HC711E9CFNE2 Freescale Semiconductor, MC68HC711E9CFNE2 Datasheet - Page 68

IC MCU 8BIT 512RAM 52-PLC

MC68HC711E9CFNE2

Manufacturer Part Number
MC68HC711E9CFNE2
Description
IC MCU 8BIT 512RAM 52-PLC
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheet

Specifications of MC68HC711E9CFNE2

Core Processor
HC11
Core Size
8-Bit
Speed
2MHz
Connectivity
SCI, SPI
Peripherals
POR, WDT
Number Of I /o
38
Program Memory Size
12KB (12K x 8)
Program Memory Type
OTP
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
52-PLCC
Processor Series
HC711E
Core
HC11
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI, SPI
Maximum Clock Frequency
2 MHz
Number Of Programmable I/os
38
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Operating Modes and On-Chip Memory
4.3.4 Bootstrap Mode
Technical Data
68
When the MCU is reset in special bootstrap mode, a small on-chip
read-only memory (ROM) is enabled at address $BF00–$BFFF. The
ROM contains a bootloader program and a special set of interrupt and
reset vectors. The MCU fetches the reset vector, then executes the
bootloader.
Bootstrap mode is a special variation of the single-chip mode. Bootstrap
mode allows special-purpose programs to be entered into internal
random-access memory (RAM). When bootstrap mode is selected at
reset, a small bootstrap ROM becomes present in the memory map.
Reset and interrupt vectors are located in this ROM at $BFC0–$BFFF.
The bootstrap ROM contains a small program which initializes the serial
communications interface (SCI) and allows the user to download a
program into on-chip RAM. The size of the downloaded program can be
as large as the size of the on-chip RAM. After a 4-character delay, or
after receiving the character for the highest address in RAM, control
Operating Modes and On-Chip Memory
MCU
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
R/W
AS
Figure 4-1. Address/Data Demultiplexing
E
D1
D2
D3
D4
D5
D6
D7
D8
LE
HC373
M68HC11E Family — Rev. 3.2
OE
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
WE
OE
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
MOTOROLA

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