HD64F2612FA20J Renesas Electronics America, HD64F2612FA20J Datasheet - Page 216

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HD64F2612FA20J

Manufacturer Part Number
HD64F2612FA20J
Description
IC H8S MCU FLASH 128K 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2612FA20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
43
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2612FA20J
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 2 Instruction Descriptions
2.2.57 (3)
SHAL (SHift Arithmetic Left)
Operation
Rd (left arithmetic shift)
Assembly-Language Format
SHAL.W Rd
Operand Size
Word
Description
This instruction shifts the bits in a 16-bit register Rd (destination operand) one bit to the left. The
most significant bit (bit 15) shifts into the carry flag. The least significant bit (bit 0) is cleared to 0.
Available Registers
Rd: R0 to R7, E0 to E7
Operand Format and Number of States Required for Execution
Notes
The SHAL instruction differs from the SHLL instruction in its effect on the overflow flag.
Rev. 4.00 Feb 24, 2006 page 200 of 322
REJ09B0139-0400
Register direct
Addressing
Mode
SHAL (W)
Mnemonic
SHAL.W
C
Rd
MSB
b15
Operands
Rd
. . . . . .
1st byte
1
0
Condition Code
H: Previous value remains unchanged.
N: Set to 1 if the result is negative; otherwise
Z: Set to 1 if the result is zero; otherwise
V: Set to 1 if an overflow occurs; otherwise
C: Receives the previous value in bit 15.
2nd byte
9
Instruction Format
cleared to 0.
cleared to 0.
cleared to 0.
I
rd
UI H
3rd byte
LSB
b0
U
N
0
4th byte
Shift Arithmetic
Z
V
States
No. of
C
1

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