HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 1005

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Bit 3—Output Port Enable (OPE): This bit specifies whether the output of the address bus and
bus control signals (AS, RD, HWR, LWR) is retained or set to high-impedance state in the
software standby mode, watch mode, and when making a direct transition.
Bit 3
OPE
0
1
Bits 2 to 0—Reserved: These bits always return 0 when read, and cannot be written to.
23B.2.2 System Clock Control Register (SCKCR)
SCKCR is an 8-bit readable/writable register that performs φ clock output control and medium-
speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Output Disable (PSTOP): In combination with the DDR of the applicable port,
this bit controls φ output. See section 23B.12, φ Clock Output Disable Function for details.
Bit 7
PSTOP
0
1
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Bit
Initial value
R/W
High-Speed Mode,
Medium-Speed Mode,
Subactive Mode
φ output (initial value)
Fixed high
Description
In software standby mode, watch mode, and when making a direct transition, address
bus and bus control signals are high-impedance.
In software standby mode, watch mode, and when making a direct transition, the
output state of the address bus and bus control signals is retained.
:
:
:
PSTOP
R/W
7
0
6
0
Sleep Mode,
Subsleep Mode
φ output
Fixed high
HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF, HD6432635F, HD64F2635F, HD6432634F]
5
0
Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF,
HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF,
Description
4
0
Software Standby
Mode, Watch Mode,
Direct Transition
Fixed high
Fixed high
STCS
R/W
3
0
SCK2
R/W
2
0
SCK1
Hardware Standby
Mode
High impedance
High impedance
R/W
1
0
(Initial value)
Page 955 of 1458
SCK0
R/W
0
0

Related parts for HD64F2638F20J