HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 1013

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
When the STBY pin is driven low, a transition is made to hardware standby mode.
Figure 23B-2 shows the timing for transition to and clearance of medium-speed mode.
23B.4 Sleep Mode
23B.4.1 Sleep Mode
When the SLEEP instruction is executed when the SBYCR SSBY bit = 0 and the LPWRCR
LSON bit = 0, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the
contents of the CPUís internal registers are retained. Other supporting modules do not stop.
23B.4.2 Exiting Sleep Mode
Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins.
Exiting Sleep Mode by Interrupts: When an interrupt occurs, sleep mode is exited and interrupt
exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other
than NMI are masked by the CPU.
Exiting Sleep Mode by RES pin: Setting the RES pin level Low selects the reset state. After the
stipulated reset input duration, driving the RES pin High starts the CPU performing reset
exception processing.
Exiting Sleep Mode by STBY Pin: When the STBY pin level is driven Low, a transition is made
to hardware standby mode.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
supporting module clock
Internal address bus
Bus master clock
Internal write signal
,
Figure 23B-2 Medium-Speed Mode Transition and Clearance Timing
SBYCR
HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF, HD6432635F, HD64F2635F, HD6432634F]
Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF,
HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF,
Medium-speed mode
SBYCR
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