HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 1022

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF,
H8S/2639, H8S/2638, H8S/2636,
HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF,
H8S/2630, H8S/2635 Group
HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF, HD6432635F, HD64F2635F, HD6432634F]
23B.8.2 Exiting Watch Mode
Watch mode is exited by any interrupt (WOVI interrupt, NMI pin, or IRQ0 to IRQ5), or signals at
the RES, or STBY pins.
(1) Exiting Watch Mode by Interrupts
When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or
medium-speed mode when the LPWRCR LSON bit = 0 or to subactive mode when the LSON bit
= 1. When a transition is made to high-speed mode, a stable clock is supplied to all LSI circuits
and interrupt exception processing starts after the time set in SBYCR STS2 to STS0 has elapsed.
In the case of IRQ0 to IRQ5 interrupts, no transition is made from watch mode if the
corresponding enable bit has been cleared to 0, and, in the case of interrupts from the internal
supporting modules, the interrupt enable register has been set to disable the reception of that
interrupt, or is masked by the CPU.
See section 23B.6.3, Setting Oscillation Stabilization Time after Clearing Software Standby Mode
for how to set the oscillation stabilization time when making a transition from watch mode to
high-speed mode.
(2) Exiting Watch Mode by RES pins
For exiting watch mode by the RES pins, see, Clearing with the RES pins in section 23B.6.2,
Clearing Software Standby Mode.
(3) Exiting Watch Mode by STBY pin
When the STBY pin level is driven Low, a transition is made to hardware standby mode.
23B.8.3 Notes
(1) I/O Port Status
The status of the I/O ports is retained in watch mode. Also, when the OPE bit is set to 1, the
address bus and bus control signals continue to be output. Therefore, when a High level is output,
the current consumption is not diminished by the amount of current to support the High level
output.
(2) Current Consumption when Waiting for Oscillation Stabilization
The current consumption increases during stabilization of oscillation.
Page 972 of 1458
REJ09B0103-0800 Rev. 8.00
May 28, 2010