HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 1023

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 23B Power-Down Modes [HD64F2636UF, HD6432636UF, HD64F2638UF, HD6432638UF,
H8S/2639, H8S/2638, H8S/2636,
HD64F2638WF, HD6432638WF, HD64F2639UF, HD6432639UF, HD64F2639WF, HD6432639WF,
H8S/2630, H8S/2635 Group
HD64F2630UF, HD6432630UF, HD64F2630WF, HD6432630WF, HD6432635F, HD64F2635F, HD6432634F]
23B.9 Subsleep Mode (U-Mask, W-Mask Version, H8S/2635 Group Only)
23B.9.1 Subsleep Mode
When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1,
and TCSR (WDT1) PSS bit = 1, CPU operation shifts to subsleep mode.
In subsleep mode, the CPU is stopped. Supporting modules other than WDT0, and WDT1 are also
stopped. The contents of the CPU’s internal registers, the data in internal RAM, and the statuses of
the internal supporting modules (excluding the SCI, ADC, HCAN, and Motor control PWM) and
I/O ports are retained.
23B.9.2 Exiting Subsleep Mode
Subsleep mode is exited by an interrupt (interrupts from internal supporting modules, NMI pin, or
IRQ0 to IRQ5), or signals at the RES or STBY pins.
(1) Exiting Subsleep Mode by Interrupts
When an interrupt occurs, subsleep mode is exited and interrupt exception processing starts.
In the case of IRQ0 to IRQ5 interrupts, subsleep mode is not cancelled if the corresponding
enable bit has been cleared to 0, and, in the case of interrupts from the internal supporting
modules, the interrupt enable register has been set to disable the reception of that interrupt, or is
masked by the CPU.
(2) Exiting Subsleep Mode by RES
For exiting subsleep mode by the RES pins, see, Clearing with the RES pins in section 23B.6.2,
Clearing Software Standby Mode.
(3) Exiting Subsleep Mode by STBY Pin
When the STBY pin level is driven Low, a transition is made to hardware standby mode.
REJ09B0103-0800 Rev. 8.00
Page 973 of 1458
May 28, 2010