HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 127

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
2.10
2.10.1
Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS
instruction is not generated by the Renesas Electronics H8S Family and H8/300 Series C/C++
compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only
register ER0, ER1, ER4, or ER5 is used.
2.10.2
With STM and LDM instructions, register ER7 cannot be used as a register that can be saved
(STM) or restored (LDM) since it is the stack pointer.
The number of registers that can be saved (STM) or restored (LDM) by a single instruction is two,
three, or four. The registers that can be used in these cases are as follows.
Two registers: ER0–ER1, ER2–ER3, ER4–ER5
Three registers: ER0–ER2, ER4–ER6
Four registers: ER0–ER3
The Renesas Electronics H8S Family and H8/300 Series C/C++ compilers do not generate
STM/LDM instructions that include ER7.
2.10.3
The BSET, BCLR, BNOT, BST, and BIST instructions read data in a unit of byte, then, after bit
manipulation, they write data in a unit of byte. Therefore, caution must be exercised when
executing any of these instructions for registers and ports that include write-only bits.
The BCLR instruction can be used to clear the flag of an internal I/O register to 0. In that case, if it
is clearly known that the pertinent flag is set to 1 in an interrupt processing routine or other
processing, there is no need to read the flag in advance.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Usage Note
TAS Instruction
STM/LDM Instructions
Caution to Observe when Using Bit Manipulation Instructions
Page 77 of 1458
Section 2 CPU