HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 143

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
4.1
4.1.1
As table 4-1 indicates, exception handling may be caused by a reset, trace, direct transition * , trap
instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more
exceptions occur simultaneously, they are accepted and processed in order of priority. Trap
instruction exceptions are accepted at all times, in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR.
Note: * Subclock functions (subactive mode, subsleep mode, and watch mode) are available in the
Table 4-1
Priority
High
Low
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
REJ09B0103-0800 Rev. 8.00
May 28, 2010
U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot be used
with the other versions.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
3. Trap instruction exception handling requests are accepted at all times in program
4. Subclock functions (subactive mode, subsleep mode, and watch mode) are available in
Overview
Exception Handling Types and Priority
Exception Type
Reset
Trace *
Direct transition *
Interrupt
Trap instruction (TRAPA) *
executed after execution of an RTE instruction.
instruction execution, or on completion of reset exception handling.
execution state.
the U-mask and W-mask versions, and H8S/2635 Group only. These functions cannot
be used with the other versions.
Supported by the H8S/2635.
Exception Types and Priority
1
Section 4 Exception Handling
4
3
Start of Exception Handling
Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog overflows. The CPU enters the
reset state when the RES pin is low.
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit is set to 1
Starts when a direct transition occurs due to execution of a
SLEEP instruction.
handling ends, if an interrupt request has been issued *
Started by execution of a trap instruction (TRAPA)
Starts when execution of the current instruction or exception
Section 4 Exception Handling
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