HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 1434

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Appendix B Internal I/O Register
TCSR0—Timer Control/Status Register 0
Page 1384 of 1458
Notes: TCSR0 register differs from other registers in being more difficult to write to.
Bit
Initial value
Read/Write
For details see section 12.2.4, Notes on Register Access.
* Only 0 can be written, to clear the flag.
Note: * When interval timer interrupts are disabled and OVF is polled,
Overflow Flag
0
1
[Clearing conditions]
• Write 0 in the TME bit (Only applies to WDT1)
• Read TCSR* when OVF = 1, then write 0 in OVF
[Setting condition]
• When TCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog timer mode,
OVF is cleared automatically by the internal reset)
R/(W)*
OVF
read the OVF = 1 state at least twice.
7
0
Note: * For details see section 12.2.3, Reset Control/Status Register (RSTCSR).
Timer Mode Select
0
1
Interval timer mode: WDT0 requests an interval timer interrupt (WOVI) from
the CPU when the TCNT overflows
Watchdog timer mode: A reset is issued when the TCNT overflows if the
RSTE bit of RSTCSR is set to 1*
WT/IT
R/W
6
0
Timer Enable
0
1
TCNT is initialized to H'00 and halted
TCNT counts
TME
R/W
5
0
Note: * An overflow period is the time interval between the
Clock Select 2 to 0
CKS2 CKS1 CKS0
0
1
⎯
⎯
4
1
start of counting up from H'00 on the TCNT and the
occurrence of a TCNT overflow.
0
1
0
1
H'FF74(W), H'FF74(R)
0
1
0
1
0
1
0
1
⎯
⎯
3
1
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock
CKS2
R/W
2
0
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
CKS1
R/W
(where φ = 20 MHz)
1
0
Overflow Period*
25.6 μs
819.2 μs
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
CKS0
R/W
0
0
May 28, 2010
WDT0