HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 1439

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
SMR0—Serial Mode Register 0
SMR1—Serial Mode Register 1
SMR2—Serial Mode Register 2
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Bit
Initial value
Read/Write
GSM Mode
Note: etu: Elementary time unit (time for transfer of 1 bit)
0
1
Normal smart card interface mode operation
• TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit
• Clock output ON/OFF control only
GSM mode smart card interface mode operation
• TEND flag generation 11.0 etu after beginning of start bit
• High/Low fixing control possible in addition to clock output ON/OFF control (set by SCR)
Note: etu: Elementary time unit (time for transfer of 1 bit)
Block Transfer Mode
0
1
R/W
GM
7
0
Normal Smart Card interface mode operation
• Error signal transmission/detection and automatic data retransmission performed
• TXI interrupt generated by TEND flag
• TEND flag set 12.5 etu after start of transmission (11.0 etu in GSM mode)
Block transfer mode operation
• Error signal transmission/detection and automatic data retransmission not performed
• TXI interrupt generated by TDRE flag
• TEND flag set 11.5 etu after start of transmission (11.0 etu in GSM mode)
R/W
BLK
6
0
R/W
Parity Enable
PE
0
1
5
0
Parity bit addition and checking disabled
Parity bit addition and checking enabled
R/W
O/E
Parity Mode
4
0
0
1
Even parity
Odd parity
Basic Clock Pulse
0
1
BCP1
R/W
H'FF78
H'FF80
H'FF88
3
0
0
1
0
1
Clock Select 1 and 0
*
0
1
32 clock periods
64 clock periods
372 clock periods
256 clock periods
*
3
2
0
1
0
1
BCP0
R/W
2
0
φ clock
φ/4 clock
φ/16 clock
φ/64 clock
Smart Card Interface 0
Smart Card Interface 1
Smart Card Interface 2
Appendix B Internal I/O Register
CKS1
*
R/W
1
1
0
Page 1389 of 1458
CKS0
R/W
0
0