HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 155

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
5.1
5.1.1
The chip controls interrupts by means of an interrupt controller. The interrupt controller has the
following features:
• Two interrupt control modes
• Priorities settable with IPR
• Independent vector addresses
• Seven external interrupts
• DTC control *
Note: * The H8S/2635 Group is not equipped with a DTC.
REJ09B0103-0800 Rev. 8.00
May 28, 2010
⎯ Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in
⎯ An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority
⎯ NMI is assigned the highest priority level of 8, and can be accepted at all times.
⎯ All interrupt sources are assigned independent vector addresses, making it unnecessary for
⎯ NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling
⎯ Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ5
⎯ DTC activation is performed by means of interrupts.
the system control register (SYSCR).
levels can be set for each module for all interrupts except NMI.
the source to be identified in the interrupt handling routine.
edge can be selected for NMI.
to IRQ0.
Overview
Features
Section 5 Interrupt Controller
Section 5 Interrupt Controller
Page 105 of 1458

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