HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 180

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
Section 5 Interrupt Controller
Table 5-10 Number of States in Interrupt Handling Routine Execution Statuses
Symbol
Instruction fetch
Branch address read
Stack manipulation
Legend:
m: Number of wait states in an external device access.
5.5
5.5.1
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction.
In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or
MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will
still be enabled on completion of the instruction, and so interrupt exception handling for that
interrupt will be executed on completion of the instruction. However, if there is an interrupt
request of higher priority than that interrupt, interrupt exception handling will be executed for the
higher-priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 5-8 shows an example in which the TCIEV bit in the TPU’s TIER register is cleared to 0.
Page 130 of 1458
Usage Notes
Contention between Interrupt Generation and Disabling
S
S
S
I
J
K
Internal
Memory
1
2-State
Access
4
8 Bit Bus
Object of Access
3-State
Access
6 + 2m
External Device
H8S/2639, H8S/2638, H8S/2636,
2-State
Access
2
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
16 Bit Bus
3-State
Access
3 + m
May 28, 2010

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