HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 20

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
Item
21C.9.4 Erase-Verify
Mode
Figure 21C-13
Erase/Erase-Verify
Flowchart
21C.13
Mode
23A.1 Overview
Page xx of l
Programmer
Page
886
894
925
Revision (See Manual for Details)
Figure amended
Title amended and description replaced
Notes: 1. Subclock functions (subactive mode, subsleep
Notes amended
Increment
address
mode, and watch mode) are available in the U-mask
and W-mask versions, and H8S/2635 Group.
These functions cannot be used with the other
versions.
NG
NG
Set block start address as verify address
H'FF dummy write to verify address
Clear ESU bit in FLMCR1
Clear SWE bit in FLMCR1
Set SWE bit in FLMCR1
Set ESU bit in FLMCR1
Clear EV bit in FLMCR1
*4
Clear E bit in FLMCR1
Set EV bit in FLMCR1
Last address of block?
All erase block erased?
Set E bit in FLMCR1
Set EBR1 or EBR2
Verify data = all 1s?
Read verify data
End of erasing
Wait (t
Wait (t
Wait (t
Wait (t
Wait (t
Wait (t
Disable WDT
Wait (t
Wait (t
Enable WDT
Wait (t
n = 1
Start
sswe
cswe
sesu
cesu
sevr
sev
cev)
se
ce
OK
OK
OK
) ms
) μs
) μs
) μs
) μs
) μs
) μs
) μs
μs
*1
NG
*5
*3 *4
*5
Start of erase
*5
Erase halted
*5
*5
*5
*5
*2
*5
*5
REJ09B0103-0800 Rev. 8.00
Clear SWE bit in FLMCR1
Clear EV bit in FLMCR1
Wait (t
Wait (t
Erase failure
n ≥ (N)?
cswe
cev
OK
) μs
) μs
*5
May 28, 2010
NG
n ← n + 1
*5
*5

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