HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 303

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
9.6.2
Table 9-8 shows the port A register configuration.
Table 9-8
Name
Port A data direction register
Port A data register
Port A register
Port A MOS pull-up control register
Port A open-drain control register
Notes: 1. Lower 16 bits of the address.
Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read.
Bits 7 to 4 are reserved; they return an undetermined value if read.
PADDR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode. The OPE bit in SBYCR is used to select whether the address
output pins retain their output state or become high-impedance when a transition is made to
software standby mode.
• Modes 4 to 6
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Bit
Initial value :
R/W
The corresponding port A pins become address outputs in accordance with the setting of bits
AE3 to AE0 in PFCR, irrespective of the value of bits PA3DDR to PA0DDR. When pins are
not used as address outputs, setting a PADDR bit to 1 makes the corresponding port A pin an
output port, while clearing the bit to 0 makes the pin an input port.
2. Value of bits 3 to 0.
Register Configuration
Port A Registers
:
:
Undefined Undefined Undefined Undefined
—
—
7
—
—
6
PADDR
Abbreviation
PADR
PORTA
PAPCR
PAODR
—
—
5
—
—
4
R/W
W
R/W
R
R/W
R/W
PA3DDR PA2DDR PA1DDR PA0DDR
W
3
0
Initial Value *
H'0
H'0
Undefined
H'0
H'0
W
2
0
2
W
1
0
Section 9 I/O Ports
Address *
H'FE39
H'FF09
H'FFB9
H'FF40
H'FF47
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W
0
0
1