HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 31

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
4.3
4.4
4.5
4.6
4.7
Section 5 Interrupt Controller
5.1
5.2
5.3
5.4
5.5
5.6
REJ09B0103-0800 Rev. 8.00
May 28, 2010
4.2.3
4.2.4
Traces................................................................................................................................ 99
Interrupts ........................................................................................................................... 100
Trap Instruction................................................................................................................. 101
Stack Status after Exception Handling.............................................................................. 102
Notes on Use of the Stack ................................................................................................. 103
Overview........................................................................................................................... 105
5.1.1
5.1.2
5.1.3
5.1.4
Register Descriptions ........................................................................................................ 108
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Interrupt Sources ............................................................................................................... 114
5.3.1
5.3.2
5.3.3
Interrupt Operation............................................................................................................ 120
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
Usage Notes ...................................................................................................................... 130
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
DTC Activation by Interrupt............................................................................................. 133
5.6.1
5.6.2
Interrupts after Reset............................................................................................ 98
State of On-Chip Supporting Modules after Reset Release ................................. 99
Features................................................................................................................ 105
Block Diagram..................................................................................................... 106
Pin Configuration................................................................................................. 107
Register Configuration......................................................................................... 107
System Control Register (SYSCR) ...................................................................... 108
Interrupt Priority Registers A to H, J to M (IPRA to IPRH, IPRJ to IPRM) ....... 109
IRQ Enable Register (IER) .................................................................................. 110
IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 111
IRQ Status Register (ISR).................................................................................... 112
External Interrupts ............................................................................................... 114
Internal Interrupts ................................................................................................ 116
Interrupt Exception Handling Vector Table......................................................... 116
Interrupt Control Modes and Interrupt Operation ................................................ 120
Interrupt Control Mode 0 ..................................................................................... 124
Interrupt Control Mode 2 ..................................................................................... 126
Interrupt Exception Handling Sequence .............................................................. 128
Interrupt Response Times .................................................................................... 129
Contention between Interrupt Generation and Disabling..................................... 130
Instructions that Disable Interrupts ...................................................................... 131
Times when Interrupts Are Disabled ................................................................... 131
Interrupts during Execution of EEPMOV Instruction.......................................... 132
IRQ Interrupts ...................................................................................................... 132
Notes on Use of NMI Interrupt ............................................................................ 132
Overview.............................................................................................................. 133
Block Diagram..................................................................................................... 133
.......................................................................................... 105
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