HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 311

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
9.7.2
Table 9-11 shows the port B register configuration.
Table 9-11 Port B Registers
Name
Port B data direction register
Port B data register
Port B register
Port B MOS pull-up control register
Port B open-drain control register
Note: * Lower 16 bits of the address.
Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.
PBDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode. The OPE bit in SBYCR is used to select whether the address output pins
retain their output state or become high-impedance when a transition is made to software standby
mode.
• Modes 4 to 6
• Mode 7
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Bit
Initial value :
R/W
The corresponding port B pins become address outputs in accordance with the setting of bits
AE3 to AE0 in PFCR, irrespective of the value of the PBDDR bits. When pins are not used as
address outputs, setting a PBDDR bit to 1 makes the corresponding port B pin an output port,
while clearing the bit to 0 makes the pin an input port.
Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing
the bit to 0 makes the pin an input port.
Register Configuration
:
:
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
W
7
0
W
6
0
Abbreviation
PBDDR
PBDR
PORTB
PBPCR
PBODR
W
5
0
W
4
0
R/W
W
R/W
R
R/W
R/W
W
3
0
Initial Value
H'00
H'00
Undefined
H'00
H'00
W
2
0
W
1
0
Section 9 I/O Ports
Address *
H'FE3A
H'FF0A
H'FFBA
H'FF41
H'FE48
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W
0
0