HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 33

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
7.4
7.5
7.6
7.7
7.8
7.9
Section 8 Data Transfer Controller (DTC)
8.1
8.2
8.3
REJ09B0103-0800 Rev. 8.00
May 28, 2010
Basic Bus Interface ........................................................................................................... 167
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
Burst ROM Interface......................................................................................................... 179
7.5.1
7.5.2
7.5.3
Idle Cycle .......................................................................................................................... 181
7.6.1
7.6.2
Write Data Buffer Function .............................................................................................. 186
Bus Arbitration.................................................................................................................. 187
7.8.1
7.8.2
7.8.3
Resets and the Bus Controller ........................................................................................... 188
Overview........................................................................................................................... 189
8.1.1
8.1.2
8.1.3
Register Descriptions ........................................................................................................ 192
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
Operation .......................................................................................................................... 200
8.3.1
8.3.2
8.3.3
8.3.4
Overview.............................................................................................................. 167
Data Size and Data Alignment............................................................................. 167
Valid Strobes........................................................................................................ 169
Basic Timing........................................................................................................ 170
Wait Control ........................................................................................................ 178
Overview.............................................................................................................. 179
Basic Timing........................................................................................................ 179
Wait Control ........................................................................................................ 181
Operation ............................................................................................................. 181
Pin States During Idle Cycles .............................................................................. 185
Overview.............................................................................................................. 187
Operation ............................................................................................................. 187
Bus Transfer Timing ............................................................................................ 187
Features................................................................................................................ 189
Block Diagram..................................................................................................... 190
Register Configuration......................................................................................... 191
DTC Mode Register A (MRA) ............................................................................ 192
DTC Mode Register B (MRB)............................................................................. 194
DTC Source Address Register (SAR).................................................................. 195
DTC Destination Address Register (DAR).......................................................... 195
DTC Transfer Count Register A (CRA) .............................................................. 195
DTC Transfer Count Register B (CRB)............................................................... 196
DTC Enable Registers (DTCER) ......................................................................... 196
DTC Vector Register (DTVECR)........................................................................ 197
Module Stop Control Register A (MSTPCRA) ................................................... 199
Overview.............................................................................................................. 200
Activation Sources ............................................................................................... 202
DTC Vector Table ............................................................................................... 204
Location of Register Information in Address Space ............................................ 208
................................................................... 189
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