HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 344

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 9 I/O Ports
9.11.2
Table 9-20 shows the port F register configuration.
Table 9-20 Port F Registers
Name
Port F data direction register
Port F data register
Port F register
Notes: 1. Lower 16 bits of the address.
Port F Data Direction Register (PFDDR)
Modes 4 to 6
Mode 7
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a reset, and in hardware standby mode, to B'10000**0 in modes 4 to 6,
and to B'00000**0 in mode 7. It retains its prior state in software standby mode. The OPE bit in
SBYCR is used to select whether the bus control output pins retain their output state or become
high-impedance when a transition is made to software standby mode.
• Modes 4 to 6
Page 294 of 1458
Bit
Initial value :
R/W
Initial value :
R/W
Pin PF7 functions as the φ output pin when the corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
The input/output direction specified by PFDDR is ignored for pins PF6 to PF3, which are
automatically designated as bus control outputs (AS, RD, HWR, and LWR) (in the 8-bit mode,
pin PF3 is designated by PFDDR).
2. Initial value depends on the mode.
Register Configuration
:
:
:
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR
W
W
7
1
0
W
W
6
0
0
Abbreviation R/W
PFDDR
PFDR
PORTF
W
W
5
0
0
W
R/W
R
W
W
4
0
0
Initial Value
B'10000**0 *
B'00000**0 *
B'00000**0
Undefined
W
W
3
0
0
undefined undefined
undefined undefined
2
2
/
—
—
—
2
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
Address *
H'FE3E
H'FF0E
H'FFBE
—
—
—
1
May 28, 2010
PF0DDR
1
W
W
0
0
0