HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 40

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16.3 Operation .......................................................................................................................... 651
16.4 CAN Bus Interface............................................................................................................ 676
16.5 Usage Notes ...................................................................................................................... 677
Section 17 A/D Converter
17.1 Overview........................................................................................................................... 681
17.2 Register Descriptions ........................................................................................................ 685
Page xl of l
16.2.4 Mailbox Configuration Register (MBCR) ........................................................... 624
16.2.5 Transmit Wait Register (TXPR) .......................................................................... 625
16.2.6 Transmit Wait Cancel Register (TXCR).............................................................. 626
16.2.7 Transmit Acknowledge Register (TXACK) ........................................................ 627
16.2.8 Abort Acknowledge Register (ABACK) ............................................................. 628
16.2.9 Receive Complete Register (RXPR).................................................................... 629
16.2.10 Remote Request Register (RFPR) ....................................................................... 630
16.2.11 Interrupt Register (IRR)....................................................................................... 631
16.2.12 Mailbox Interrupt Mask Register (MBIMR) ....................................................... 636
16.2.13 Interrupt Mask Register (IMR) ............................................................................ 637
16.2.14 Receive Error Counter (REC) .............................................................................. 640
16.2.15 Transmit Error Counter (TEC)............................................................................. 640
16.2.16 Unread Message Status Register (UMSR)........................................................... 641
16.2.17 Local Acceptance Filter Masks (LAFML, LAFMH)........................................... 642
16.2.18 Message Control (MC0 to MC15) ....................................................................... 644
16.2.19 Message Data (MD0 to MD15) ........................................................................... 648
16.2.20 Module Stop Control Register C (MSTPCRC).................................................... 650
16.3.1 Hardware and Software Resets ............................................................................ 651
16.3.2 Initialization after Hardware Reset ...................................................................... 654
16.3.3 Transmit Mode..................................................................................................... 659
16.3.4 Receive Mode ...................................................................................................... 665
16.3.5 HCAN Sleep Mode.............................................................................................. 671
16.3.6 HCAN Halt Mode................................................................................................ 673
16.3.7 Interrupt Interface ................................................................................................ 673
16.3.8 DTC Interface ...................................................................................................... 675
17.1.1 Features................................................................................................................ 681
17.1.2 Block Diagram..................................................................................................... 682
17.1.3 Pin Configuration................................................................................................. 683
17.1.4 Register Configuration......................................................................................... 684
17.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 685
17.2.2 A/D Control/Status Register (ADCSR) ............................................................... 686
17.2.3 A/D Control Register (ADCR) ............................................................................ 689
17.2.4 Module Stop Control Register A (MSTPCRA) ................................................... 690
................................................................................................. 681
REJ09B0103-0800 Rev. 8.00
May 28, 2010