HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 486

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 12 Watchdog Timer
12.2.3
Note: * Can only be written with 0 for flag clearing.
RSTCSR is an 8-bit readable/writable * register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal
reset signal caused by overflows.
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details
Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from
H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode.
Bit 7
WOVF
0
1
Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the
H8S/2636 if TCNT overflows during watchdog timer operation.
Bit 6
RSTE
0
1
Note: * The modules within the chip are not reset, but TCNT and TCSR within the WDT are reset.
Page 436 of 1458
Bit
Initial value :
R/W
see section 12.2.4, Notes on Register Access.
Reset Control/Status Register (RSTCSR)
Description
[Clearing condition]
•
[Setting condition]
•
Description
Reset signal is not generated if TCNT overflows *
Reset signal is generated if TCNT overflows
:
:
Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF
Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer
operation
R/(W) *
WOVF
7
0
RSTE
R/W
6
0
RSTS
R/W
5
0
—
—
4
1
—
—
3
1
—
—
2
1
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
—
—
1
1
(Initial value)
(Initial value)
May 28, 2010
—
—
0
1