HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 583

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
Section 14 Smart Card Interface
Serial Data Transmission (Except Block Transfer Mode): As data transmission in smart card
mode involves error signal sampling and retransmission processing, the processing procedure is
different from that for the normal SCI. Figure 14-4 shows a flowchart for transmitting, and figure
14-5 shows the relation between a transmit operation and the internal registers.
[1] Perform Smart Card interface mode initialization as described above in initialization.
[2] Check that the ERS error flag in SSR is cleared to 0.
[3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1.
[4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation.
The TEND flag is cleared to 0.
[5] When transmitting data continuously, go back to step [2].
[6] To end transmission, clear the TE bit to 0.
With the above processing, interrupt servicing or data transfer by the DTC is possible.
If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt
requests are enabled, a transmit data empty interrupt (TXI) request will be generated. If an error
occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt
requests are enabled, a transfer error interrupt (ERI) request will be generated.
The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag
set timing is shown in figure 14-6.
If the DTC * is activated by a TXI request, the number of bytes set in the DTC * can be transmitted
automatically, including automatic retransmission.
For details, see Interrupt Operation and Data Transfer Operation by DTC below.
Notes: For block transfer mode, see section 13.3.2, Operation in Asynchronous Mode.
* The DTC is not implemented in the H8S/2635 Group.
REJ09B0103-0800 Rev. 8.00
Page 533 of 1458
May 28, 2010

Related parts for HD64F2638F20J