HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 628

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
Section 15 I
(Only for the H8S/2638, H8S/2639, and H8S/2630)
15.3.2
At startup the following procedure is used to initialize the IIC.
Note: The ICMR register should be written to only after transmit or receive operations have
15.3.3
In I
data, and the slave device returns an acknowledge signal.
Figure 15-7 is a flowchart showing an example of the master transmit mode.
Page 578 of 1458
2
C bus format master transmit mode, the master device outputs the transmit clock and transmit
completed.
Writing to the ICMR register while a transmit or receive operation is in progress could
cause an erroneous value to be written to bit counter bits BC2 to BC0. This could result in
improper operation.
Initial Setting
Master Transmit Operation
2
C Bus Interface [Option]
Set MSTP4 = 0 (IIC0)
Transmit/receive start
Set IICE = 1 (SCRX)
Set SAR and SARX
Set ICE = 0 (ICCR)
Set ICE = 1 (ICCR)
MSTP3 = 0 (IIC1)
Start initialization
(MSTPCRB)
Set SCRX
Set IMCR
Set ICSR
Set ICCR
Figure 15-6 Flowchart for IIC Initialization (Example)
Clear module stop
Enable CPU access by IIC control register and data register
Enable SAR and SARX access
Set transfer format for 1st slave address, 2nd slave address,
and IIC (SVA8−SVA0, FS, SVAX6−SVAX0, FSX)
Enable IMCR and IMDR access. Use SCL and SDA pins is IIC
port
Set acknowledge bit (ACKB)
Set transfer rate (IICX)
Set transfer format, wait insertion, and transfer rate (MLS,
WAIT, CKS2−CKS0)
Set interrupt enable, transfer mode, and acknowledge
judgment (IEIC, MST, TRS, ACKE)
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
May 28, 2010

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