HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 635
HD64F2638F20J
Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Specifications of HD64F2638F20J
Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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H8S/2639, H8S/2638, H8S/2636,
H8S/2630, H8S/2635 Group
[1] Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the
[2] When ICDR is read (dummy data read), reception is started, and the receive clock is output,
[3] The IRIC flag is set to 1 by the following two conditions. At that point, an interrupt request is
[4] Read the IRTR flag in ICSR. If the IRTR flag value is 0, the wait state is cancelled by
[5] If the IRTR flag value is 1, read the ICDR receive data.
[6] Clear the IRTR flag to 0. If condition [3]-1 is true, the master device drives SDA to low level
[7] Set the ACKB bit in ICSR to 1 to set the acknowledge data for the final receive.
[8] Wait for at least 1 clock cycle after the IRIC flag is set to 1 and then wait for the rising edge
[9] Set the TSR bit in ICCR to 1 to switch from the receive mode to the transmit mode. The TSR
[10] Read the ICDR receive data.
[11] Clear the IRTR flag to 0.
[12] The IRIC flag is set to 1 by the following two conditions.
[13] Read the IRTR flag in ICSR. If the IRTR flag value is 0, the wait state is cancelled by
REJ09B0103-0800 Rev. 8.00
May 28, 2010
ACKB bit in ICSR to 0 (acknowledge data setting). Clear the IRIC flag to 0, then set the
WAIT bit in ICMR to 1.
and data received, in synchronization with the internal clock.
issued to the CPU if the IEIC bit in ICCR is set to 1.
1. The flag is set at the falling edge of the 8th clock cycle of the receive clock for 1 frame.
2. The flag is set at the rising edge of the 9th clock cycle of the receive clock for 1 frame.
clearing the IRIC flag as described in step [6] below. If the IRTR flag value is 1 and the next
receive data is the final receive data, perform the end processing described in step [7] below.
and returns an acknowledge signal when the receive clock outputs the 9th clock cycle.
Further data can be received by repeating steps [3] through [6].
of the 1st clock cycle of the next receive data.
bit setting value at this point becomes valid when the rising edge of the next 9th clock cycle
is input.
1. The flag is set at the falling edge of the 8th clock cycle of the receive clock for 1 frame.
2. The flag is set at the rising edge of the 9th clock cycle of the receive clock for 1 frame.
clearing the IRIC flag as described in step [14] below. If the IRTR flag value is 1 and the
SCL is automatically held low, in synchronization with the internal clock, until the IRIC
flag is cleared.
The IRIC flag and ICDRF flag are set to 1, indicating that reception of 1 frame of data has
ended. The master device continues to output the receive clock for the receive data.
SCL is automatically held low, in synchronization with the internal clock, until the IRIC
flag is cleared.
The IRIC flag and ICDRF flag are set to 1, indicating that reception of 1 frame of data has
ended. The master device continues to output the receive clock for the receive data.
(Only for the H8S/2638, H8S/2639, and H8S/2630)
Section 15 I
2
C Bus Interface [Option]
Page 585 of 1458
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