HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 646

• Manufacturer Part Number: HD64F2638F20J
• Description: IC H8S MCU FLASH 256K 128-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of HD64F2638F20J

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SmartCard
• Peripherals: Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 15 I
(Only for the H8S/2638, H8S/2639, and H8S/2630)
15.3.8
The I
the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication
of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out
in conjunction with CPU processing by means of interrupts.
Table 15-5 shows some examples of processing using the DTC. These examples assume that the
number of transfer data bytes is known in slave mode.
Table 15-5 Examples of Operation Using the DTC
Item
Slave address +
R/W bit
transmission/
reception
Dummy data
read
Actual data
transmission/
reception
Dummy data
(H'FF) write
Last frame
processing
Transfer request
processing after
last frame
processing
Setting of
number of DTC
transfer data
frames
Page 596 of 1458
2
C bus format provides for selection of the slave device and transfer direction by means of
Operation Using the DTC
2
C Bus Interface [Option]
Master Transmit
Mode
Transmission by
DTC (ICDR write)
—
Transmission by
DTC (ICDR write)
—
Not necessary
1st time: Clearing
by CPU
2nd time: End
condition issuance
by CPU
Transmission:
Actual data count
+ 1 (+1 equivalent
to slave address +
R/W bits)
Master Receive
Mode
Transmission by
CPU (ICDR write)
Processing by
CPU (ICDR read)
Reception by
DTC (ICDR read)
—
Reception by
CPU (ICDR read)
Not necessary
Reception: Actual
data count
Slave Transmit
Mode
Reception by
CPU (ICDR read)
—
Transmission by
DTC (ICDR write)
Processing by
DTC (ICDR write)
Not necessary
Automatic clearing
on detection of end
condition during
transmission of
dummy data (H'FF)
Transmission:
Actual data count
+ 1 (+1 equivalent
to dummy data
(H'FF))
H8S/2639, H8S/2638, H8S/2636,
REJ09B0103-0800 Rev. 8.00
H8S/2630, H8S/2635 Group
Slave Receive
Mode
Reception by CPU
(ICDR read)
—
Reception by DTC
(ICDR read)
—
Reception by CPU
(ICDR read)
Not necessary
Reception: Actual
data count
May 28, 2010